# US 10,481,958 B2 · Speculative execution tag for asynchronous DRAM refresh

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- Number: US 10,481,958 B2
- Document ID: US10481958B2
- Status: Granted
- Kind: B2
- Application number: 15/858,732
- Filed: 2017-12-29
- Published: 2019-02-07
- Granted: 2019-11-19
- Earliest claimed: 2017-12-29
- Assignees: Intel IP Corporation
- Applicants: Intel IP Corporation
- Inventors: Thomas Willhalm; Karthik Kumar
- Web page: https://patentgrep.com/patent/US10481958B2

## CPC

- G06F 9/528: {by using speculative mechanisms}
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
- G06F 12/128: adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
- G06F 2212/1016: Performance improvement
- G06F 2212/621: Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An embodiment of a semiconductor package apparatus may include technology to track a modification to a processor cache line, and set an indicator to indicate if the modification relates to a transaction. Other embodiments are disclosed and claimed.

## Claims

### Claim 1

An electronic processing system, comprising:
a processor;
persistent memory communicatively coupled to the processor; and
logic communicatively coupled to the processor to:
track a modification to a cache line of the processor;
set an indicator to indicate if the modification relates to a transaction, and set the indicator to indicate if the modification relates to a speculative execution corresponding to the transaction;
detect a power transition;
determine if an address of the processor cache line corresponds to an application direct address range, in response to the detected power transition; and
flush the processor cache line to the persistent memory based on a state of the indicator indicating whether the modification relates to a speculative execution and in response to the detected power transition.

### Claim 2 (depends on 1)

The system of claim 1, wherein the logic is further to:
flush the processor cache line to the persistent memory based on a state of the indicator indicating whether the modification relates to a speculative execution and in response to the detected power transition, if the processor cache line address is determined to correspond to the application direct address range.

### Claim 3 (depends on 1)

The system of claim 1, wherein the indicator comprises a bit of the processor cache line.

### Claim 4 (depends on 1)

The system of claim 1, wherein the transaction corresponds to a transactional memory transaction.

### Claim 5

A semiconductor package apparatus, comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
track a modification to a processor cache line;
set an indicator to indicate if the modification relates to a transaction, and set the indicator to indicate if the modification relates to a speculative execution corresponding to the transaction;
detect a power transition;
determine if an address of the processor cache line corresponds to an application direct address range, in response to the detected power transition; and
flush the processor cache line to the persistent memory based on a state of the indicator indicating whether the modification relates to a speculative execution and in response to the detected power transition.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the logic is further to:
flush the processor cache line to persistent memory based on a state of the indicator indicating whether the modification relates to a speculative execution and in response to the detected power transition, if the processor cache line address is determined to correspond to the application direct address range.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the indicator comprises a bit of the processor cache line.

### Claim 8 (depends on 5)

The apparatus of claim 5, wherein the transaction corresponds to a transactional memory transaction.

### Claim 9

A method of tracking a cache line modification, comprising:
tracking a modification to a processor cache line;
setting an indicator to indicate if the modification relates to a transaction, and setting the indicator to indicate if the modification relates to a speculative execution corresponding to the transaction;
detecting a power transition;
determining if an address of the processor cache line corresponds to an application direct address range, in response to the detected power transition; and
flushing the processor cache line to the persistent memory based on a state of the indicator indicating whether the modification relates to a speculative execution and in response to the detected power transition.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
flushing the processor cache line to persistent memory based on a state of the indicator indicating whether the modification relates to a speculative execution and in response to the detected power transition, if the processor cache line address is determined to correspond to the application direct address range.

### Claim 11 (depends on 9)

The method of claim 9, wherein the indicator comprises a bit of the processor cache line.

### Claim 12 (depends on 9)

The method of claim 9, wherein the transaction corresponds to a transactional memory transaction.

### Claim 13

At least one non-transitory computer readable medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:
track a modification to a processor cache line; and
set an indicator to indicate if the modification relates to a transaction, and set the indicator to indicate if the modification relates to a speculative execution corresponding to the transaction;
detect a power transition;
determine if an address of the processor cache line corresponds to an application direct address range, in response to the detected power transition; and
flush the processor cache line to the persistent memory based on a state of the indicator indicating whether the modification relates to a speculative execution and in response to the detected power transition.

### Claim 14 (depends on 13)

The at least one non-transitory computer readable medium of claim 13, comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
flush the processor cache line to persistent memory based on a state of the indicator indicating whether the modification relates to a speculative execution and in response to the detected power transition, if the processor cache line address is determined to correspond to the application direct address range.

### Claim 15 (depends on 13)

The at least one non-transitory computer readable medium of claim 13, wherein the indicator comprises a bit of the processor cache line.

### Claim 16 (depends on 13)

The at least one non-transitory computer readable medium of claim 13, wherein the transaction corresponds to a transactional memory transaction.