# US 10,481,923 B2 · Data processing device, processor core array and method for characterizing behavior of equipment under observation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,481,923 B2 - Document ID: US10481923B2 - Status: Granted - Kind: B2 - Application number: 16/229,283 - Filed: 2018-12-21 - Published: 2019-04-18 - Granted: 2019-11-19 - Earliest claimed: 2013-12-05 - Assignees: JDA Software, Inc. - Applicants: Blue Yonder GmbH - Inventors: Frank Kienle - Web page: https://patentgrep.com/patent/US10481923B2 ## CPC - G06F 9/44505: {Configuring for program initiating, e.g. using registry, configuration files} - G05B 19/042: using digital processors (G05B19/05 takes precedence) - G06F 11/3024: {where the computing system component is a central processing unit [CPU]} - G06F 11/3409: {for performance assessment} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G05B: CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS (systems for controlling or regulating non-electric variables G05D; systems for regulating electric or magnetic variables G05F; control devices or systems insofar as characterised by mechanical features only G05G) ## Abstract A data processing device (100) characterizes behavior properties of equipment under observation (105). The device (100) has a plurality of processing units that are adapted to process input values (a) to output values (e) according to numerical transfer functions. The functions implement an input-to-output mapping specified by a configuration (C) that is obtained by pre-processing historic data (114) from a plurality of master equipment (104). The configuration is related to the behavior properties of the equipment (105) so that some of the output values (e) represent the behavior properties of the equipment (105) under observation. ## Claims ### Claim 1 A data processing device for characterizing behavior properties of equipment under observation, the data processing device comprising: a processor core array comprising two or more processor cores configured to select processor cores of the two or more processor cores as a first processing stage and processor cores of the two or more processor cores as a second processing stage according to an availability of the processor cores and according to a presence of equipment data values from an equipment under observation, wherein the processor cores of the first processing stage receive two or more equipment data values from the equipment under observation as input and provide two or more intermediate data values as output, according to two or more first numerical transfer functions, and wherein the processor cores of the second processing stage receive the two or more intermediate data values as input and provide behavior data as output values according to a second numerical transfer function; and the selected processor cores process input values based on numerical transfer functions to output values by implementing an input-to-output mapping based on a configuration obtained by a pre-processing of historic data from two or more master equipment and related to the behavior properties of the equipment under observation. ### Claim 2 (depends on 1) The data processing device according to claim 1, further comprising causing the selected processor cores to serialize operation when a number of selected processor cores is smaller than a number of equipment data values that are simultaneously present in parallel from the equipment under observation. ### Claim 3 (depends on 2) The data processing device of claim 2, wherein the selected processor cores operate sequentially as a first processing stage and a second processing stage. ### Claim 4 (depends on 3) The data processing device of claim 3, wherein the configuration comprises a first processing stage configuration and a second processing stage configuration. ### Claim 5 (depends on 4) The data processing device of claim 4, further comprising assigning data structures in a memory to operate as configuration buffers and associates the data structures with the selected processor cores to receive the configuration. ### Claim 6 (depends on 5) The data processing device of claim 5, further comprising assigning a data structure to receive a configuration of a first processing context and to receive a configuration of a second processing context, and wherein the processor core array selects two or more processor cores to process data values accordingly. ### Claim 7 A computer-implemented method for operating a data processing device to characterize behavior properties of equipment under observation, the computer-implemented method comprising: selecting processor cores of a processor core array comprising two or more processor cores as a first processing stage and processor cores of the two or more processor cores as a second processing stage, according to an availability of the selected processor cores and according to a presence of equipment data values from an equipment under observation, wherein the processor cores of the first processing stage receive two or more equipment data values from the equipment under observation as input and provide two or more intermediate data values as output, according to two or more first numerical transfer functions, and wherein the processor cores of the second processing stage receive the two or more intermediate data values as input and provide behavior data as output values according to a second numerical transfer function; and processing input values, by the selected processor cores, based on numerical transfer functions to output values by an input-to-output mapping based on a configuration obtained by a pre-processing of historic data from two or more master equipment and related to the behavior properties of the equipment under observation. ### Claim 8 (depends on 7) The computer-implemented method of claim 7, wherein the computer-implemented method further comprises: serializing operation, by the selected processor cores, when a number of selected processor cores is smaller than a number of equipment data values that are simultaneously present in parallel from the equipment under observation. ### Claim 9 (depends on 8) The computer-implemented method of claim 8, wherein the computer-implemented method further comprises: operating sequentially the selected processor cores as a first processing stage and a second processing stage. ### Claim 10 (depends on 9) The computer-implemented method of claim 9, wherein the configuration comprises a first processing stage configuration and a second processing stage configuration. ### Claim 11 (depends on 10) The computer-implemented method of claim 10, wherein the computer-implemented method further comprises: assigning data structures in a memory to operate as configuration buffers; and associating the data structures with the selected processor cores to receive the configuration. ### Claim 12 (depends on 11) The computer-implemented method of claim 11, wherein the computer-implemented method further comprises: assigning a data structure to receive a configuration of a first processing context and to receive a configuration of a second processing context; and selecting, by the processor core array, two or more processor cores to process data values according to the configuration of the first processing context and the configuration of the second processing context. ### Claim 13 A non-transitory computer-readable medium having stored thereon a sequence of computer-executable instructions which when executed by at least one processor of a computer performs a method for controlling a data processing device, the method comprising: selecting processor cores of a processor core array comprising two or more processor cores, as a first processing stage and processor cores of the two or more processor cores as a second processing stage according to an availability of the selected processor cores and according to a presence of equipment data values from an equipment under observation, wherein the operation module selects the processor cores from the two or more processor cores according to an availability of the processor cores and according to a presence of equipment data values from an equipment under observation, wherein the processor cores of the first processing stage receive two or more equipment data values from the equipment under observation as input and provide two or more intermediate data values as output, according to two or more first numerical transfer functions, and wherein the processor cores of the second processing stage receive the two or more intermediate data values as input and provide behavior data as output values according to a second numerical transfer function; and processing input values based on numerical transfer functions to output values by an input-to-output mapping based on a configuration obtained by a pre-processing of historic data from two or more master equipment and related to the behavior properties of the equipment under observation. ### Claim 14 (depends on 13) The non-transitory computer-readable medium of claim 13, wherein the method further comprises: serializing operation of the selected processor cores when a number of selected processor cores is smaller than a number of equipment data values that are simultaneously present in parallel from the equipment under observation. ### Claim 15 (depends on 14) The non-transitory computer-readable medium of claim 14, wherein the method further comprises: operating sequentially the selected processor cores as a first processing stage and a second processing stage. ### Claim 16 (depends on 15) The non-transitory computer-readable medium of claim 15, wherein the configuration comprises a first processing stage configuration and a second processing stage configuration. ### Claim 17 (depends on 16) The non-transitory computer-readable medium of claim 16, wherein the method further comprises: assigning data structures in a memory to operate as configuration buffers; and associating the data structures with the selected processor cores to receive the configuration.