# US 10,481,913 B2 · Token-based data dependency protection for memory access

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- Number: US 10,481,913 B2
- Document ID: US10481913B2
- Status: Granted
- Kind: B2
- Application number: 15/967,619
- Filed: 2018-05-01
- Published: 2019-02-21
- Granted: 2019-11-19
- Earliest claimed: 2017-08-16
- Assignees: MediaTek Singapore Pte. Ltd.
- Applicants: MediaTek Singapore Pte. Ltd.
- Inventors: Steve Hengchen Hsu; Hsiao-Han Ma; Chia-An Lin; Wei-Lun Hung; Dan MingLun Chuang
- Web page: https://patentgrep.com/patent/US10481913B2

## CPC

- G06F 9/3834: {Maintaining memory consistency}
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/3838: {Dependency mechanisms, e.g. register scoreboarding}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A device protects data dependency for memory access. The device includes a memory and a processor. The processor executes memory access instructions including load instructions and store instructions. The processor includes load circuitry to execute the load instructions; and store circuitry to execute the store instructions. Each memory access instruction includes a token index field containing a token index that associates the memory access instruction with a memory location. The processor further includes dispatch circuitry to dispatch instructions to the load circuitry and the store circuitry; and a token registry to record used token indices according to token index fields in the memory access instructions dispatched by the dispatch circuitry.

## Claims

### Claim 1

A device operative to protect data dependency for memory access, comprising:
a memory; and
a processor coupled to the memory to execute memory access instructions including load instructions and store instructions, the processor including:
load circuitry to execute the load instructions;
store circuitry to execute the store instructions, wherein each memory access instruction includes an opcode, an operand field, and a token index field, and wherein the token index field contains a token index that associates the memory access instruction with a memory location;
dispatch circuitry to dispatch instructions to the load circuitry and the store circuitry; and
a token registry to record used token indices according to token index fields in the memory access instructions dispatched by the dispatch circuitry.

### Claim 2 (depends on 1)

The device of claim 1, wherein the load circuitry is further operative to:
check the token registry for a given token index when receiving a load instruction having the given token index; and
in response to a determination that the given token index is in use by a store instruction, place the load instruction on hold until the given token index is released at completion of the store instruction.

### Claim 3 (depends on 1)

The device of claim 1, wherein the store circuitry is further operative to:
check the token registry for a given token index when receiving a store instruction having the given token index; and
in response to a determination that the given token index is in use by a load instruction, place the store instruction on hold until the given token index is released at completion of the load instruction.

### Claim 4 (depends on 1)

The device of claim 1, wherein the token registry includes circuitry to check token indices used by the store instructions when a token check is requested by the load circuitry.

### Claim 5 (depends on 1)

The device of claim 1, wherein the token registry includes circuitry to check token indices used by the load instructions when a token check is requested by the store circuitry.

### Claim 6 (depends on 1)

The device of claim 1, wherein the dispatch circuitry is operative to dispatch an instruction having a given token index in response to a determination that the number of instructions having the given token index in a corresponding token table of the token registry does not exceed a table depth limit.

### Claim 7 (depends on 1)

The device of claim 1, further comprises a scheduler operative to schedule the memory access instructions in an instruction sequence according to respective token indices carried by the memory access instructions.

### Claim 8 (depends on 1)

The device of claim 1, wherein the token registry is operative to record token indices being used and instruction identifiers waiting for the used token indices.

### Claim 9 (depends on 1)

The device of claim 1, wherein the load circuitry and the store circuitry are operative to concurrently execute instructions having different token indices.

### Claim 10 (depends on 1)

The device of claim 1, wherein a reserved token index in the token index field of a given instruction indicates that there is no dependency with respect to memory locations to be accessed between the given instruction and other memory access instructions.

### Claim 11

A method of protecting data dependency for memory access, comprising:
receiving a memory access instruction which includes an opcode, an operand field, and a token index field, wherein the token index field contains token index that associates the memory access instruction with a memory location;
performing a token check with a token register, which records used token indices according to token index fields in memory access instructions; and
executing the memory access instruction according to the token check.

### Claim 12 (depends on 11)

The method of claim 11, wherein performing the token check further comprises:
checking the token registry for a given token index when receiving a load instruction having the given token index; and
in response to a determination that the given token index is in use by a store instruction, placing the load instruction on hold until the given token index is released at completion of the store instruction.

### Claim 13 (depends on 11)

The method of claim 11, wherein performing the token check further comprises:
checking the token registry for a given token index when receiving a store instruction having the given token index; and
in response to a determination that the given token index is in use by a load instruction, placing the store instruction on hold until the given token index is released at completion of the load instruction.

### Claim 14 (depends on 11)

The method of claim 11, wherein performing the token check further comprises:
checking the token indices used by store instructions when the token check is requested by load circuitry executing a load instruction.

### Claim 15 (depends on 11)

The method of claim 11, wherein performing the token check further comprises:
checking token indices used by load instructions when the token check is requested by store circuitry executing a store instruction.

### Claim 16 (depends on 11)

The method of claim 11, further comprising:
dispatching an instruction having a given token index in response to a determination that the number of instructions having the given token index in a corresponding token table of in the token registry does not exceed a table depth limit.

### Claim 17 (depends on 11)

The method of claim 11, further comprising:
scheduling the memory access instructions in an instruction sequence according to respective token indices carried by the memory access instructions.

### Claim 18 (depends on 11)

The method of claim 11, further comprising:
recording, in the token registry, token indices being used and instruction identifiers waiting for the used token indices.

### Claim 19 (depends on 11)

The method of claim 11, further comprising:
concurrently executing a load instruction and a store instruction that carry different token indices.

### Claim 20 (depends on 11)

The method of claim 11, wherein a reserved token index in the token index field of a given instruction indicates that there is no dependency with respect to memory locations to be accessed between the given instruction and other memory access instructions.