# US 10,481,911 B2 · Synchronization of execution threads on a multi-threaded processor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,481,911 B2
- Document ID: US10481911B2
- Status: Granted
- Kind: B2
- Application number: 14/177,980
- Filed: 2014-02-11
- Published: 2014-11-06
- Granted: 2019-11-19
- Earliest claimed: 2006-11-02
- Assignees: Imagination Technologies Limited
- Applicants: Imagination Technologies Limited
- Inventors: Yoong Chert Foo
- Web page: https://patentgrep.com/patent/US10481911B2

## CPC

- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/3851: {from multiple instruction streams, e.g. multistreaming}
- G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel}
- G06F 9/522: {Barrier synchronisation}
- G06F 9/524: {Deadlock detection or avoidance}
- G06F 8/458: {Synchronisation, e.g. post-wait, barriers, locks (synchronisation among tasks G06F9/52)}
- G06F 9/30087: {Synchronisation or serialisation instructions}
- G06F 9/3009: {Thread control instructions}
- G06F 9/461: {Saving or restoring of program or task context}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Method and apparatus are provided for synchronizing execution of a plurality of threads on a multi-threaded processor. A program executed by a thread can have a number of synchronization points corresponding to points where execution is to be synchronized with another thread. Execution of a thread is paused when it reaches a synchronization point until at least one other thread with which it is intended to be synchronized reaches a corresponding synchronization point. Execution is subsequently resumed. A control core maintains status data for threads and can cause a thread that is ready to run to use execution resources that were occupied by a thread that is waiting for a synchronization event.

## Claims

### Claim 1

A multi-threaded processor system for processing a plurality of threads, the plurality of threads comprising a group of threads, each thread of the group of threads to be synchronised with other threads in the group of threads, the multi-threaded processor system comprising:
a plurality of data processing cores configured to simultaneously execute multiple threads for a program;
an instruction decode unit configured to decode program instructions to be used to configure the plurality of data processing cores, and to generate an indication when a thread of the group of threads that is executing program instructions, which is to be synchronised with other threads of the group of threads, branches around a section of program instructions, while another thread of the group of threads does not branch around a corresponding section of program instructions; and
a control core coupled with the instruction decode unit and configured to receive the indication and to control which threads are to execute on which of the plurality of data processing cores, the control core comprising non-transitory memory configured to contain status data for the plurality of threads, of which the threads in the group of threads are a subset,
wherein a number of threads in the plurality of threads is greater than a number of threads in the group of threads that are a subset of the plurality of threads, and the status data comprises, for each thread of the group of threads, an indication whether it is waiting to be synchronised with another thread in the group of threads, and
the control core is responsive to receiving the indication, by updating the status data for the thread of the group of threads to which the indication pertains, and, where the thread of the group of threads to which the indication pertains is waiting to be synchronised with another thread of the group of threads, to swap a thread from the group of threads to be executed by the plurality of data processing cores, which is not waiting for synchronization with the thread of the group of threads to which the indication pertains, the control core being operable to swap threads executing on the plurality of processing cores on each clock cycle of a clock provided to the plurality of processing cores.

### Claim 2 (depends on 1)

The multi-threaded processor system of claim 1, wherein the non-transitory memory of the control core comprises a register for each thread of the plurality of threads.

### Claim 3 (depends on 1)

The multi-threaded processor system of claim 1, wherein the number of threads in the group of threads exceeds a number of data processing cores in the plurality of data processing cores.

### Claim 4

A multi-threaded processor system, comprising:
a plurality of data processing cores configured to synchronously execute multiple threads of a group of threads of a single program of instructions on the plurality of data processing cores;
an instruction decode unit configured to decode instructions from the program, and to determine a next instruction of the program to be executed by each of the threads of the group of threads and responsive to reaching a branch point in the program in which at least one of the threads of the group of threads branches around the branch point, to generate an indication; and
a control core coupled with the instruction decode unit and configured to receive the indication and to control which threads are to execute on which of the plurality of data processing cores, and to put the thread of the group of threads that will branch around the branch point into a wait state,
to swap in another thread of the group of threads to be synchronously executed and to resume execution after other threads of the group of threads have either branched over the branch point or execute the program instructions in the branch, the execution being synchronous for the threads of the group of threads on the plurality of data processing cores;
wherein the control core is operable to swap threads executing on the plurality of processing cores on each clock cycle of a clock provided to the plurality of processing cores.

### Claim 5 (depends on 4)

The multi-threaded processor system of claim 4, wherein the number of threads in the group of threads exceeds a number of data processing cores in the plurality of data processing cores.

### Claim 6

A method of multi-threaded processing in a multi-threaded processor, comprising:
synchronously executing multiple threads of a group of threads of a single program of instructions on a plurality of data processing cores;
decoding instructions from the program and determining a next instruction of the program to be executed by each of the threads of the group of threads;
responsive to reaching a branch point in the program, in which at least one of the threads of the group of threads is to branch around the branch point while at least one other of the threads of the group of threads is to execute the instructions branched over by the at least one of the threads of the group of threads, putting the thread of the group of threads that will branch around the branch point into a wait state; and
swapping in another thread of the group of threads to be synchronously executed, and resuming synchronous execution of the threads of the group of threads after all of the threads of the group of threads execute the same instruction of the program again;
wherein the multi-threaded processor is operable to swap threads executing on the plurality of data processing cores on each clock cycle of a clock provided to the plurality of data processing cores.

### Claim 7 (depends on 6)

The method of claim 6, wherein the putting of the thread of the group of threads that will branch around the branch point into a wait state comprises setting a bit in a status register for that thread.

### Claim 8 (depends on 7)

The method of claim 7, further comprising conditioning the resuming synchronous execution of the threads of the group of threads on availability of processing resources required to execute the threads of the group of threads.

### Claim 9 (depends on 6)

The method of claim 6, further comprising performing a thread swap process on each clock cycle of said clock provided to the plurality of processor cores.

### Claim 10 (depends on 6)

The method of claim 6, wherein a number of threads in the group of threads exceeds a number of data processing cores in the plurality of data processing cores.