# US 10,481,910 B2 · Apparatus and method for shifting quadwords and extracting packed words > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,481,910 B2 - Document ID: US10481910B2 - Status: Granted - Kind: B2 - Application number: 15/721,466 - Filed: 2017-09-29 - Published: 2019-04-04 - Granted: 2019-11-19 - Earliest claimed: 2017-09-29 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Venkateswara Madduri; Elmoustapha Ould-Ahmed-Vall; Jesus Corbal; Mark Charney; Robert Valentine; Binwei Yang - Web page: https://patentgrep.com/patent/US10481910B2 ## CPC - G06F 9/30018: {Bit or string instructions} - G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE} - G06F 9/30014: {with variable precision} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30038: {using a mask} - G06F 9/30196: {using decoder, e.g. decoder per instruction set, adaptable or programmable decoders} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus and method for performing right-shifting operations on packed quadword data. For example, one embodiment of a processor comprises: a decoder to decode a right-shift instruction to generate a decoded right-shift instruction; a first source register to store a plurality of packed quadwords data elements; execution circuitry to execute the decoded right-shift instruction, the execution circuitry comprising shift circuitry to right-shift at least first and second packed quadword data elements from first and second packed quadword data element locations, respectively, in the first source register by an amount specified in an immediate value or in a control value in a second source register, to generate first and second right-shifted quadwords; the execution circuitry to cause selection of 16 most significant bits of the first and second right-shifted quadwords to be written to 16 least significant bit regions of first and second quadword data element locations, respectively, of a destination register; and the destination register to store the specified set of the 16 most significant bits of the first and second right-shifted quadwords. ## Claims ### Claim 1 A processor comprising: a decoder to decode a right-shift instruction to generate a decoded right-shift instruction; a first source register to store a plurality of packed quadwords data elements; execution circuitry to execute the decoded right-shift instruction, the execution circuitry comprising shift circuitry to right-shift at least first and second packed quadword data elements from first and second packed quadword data element locations, respectively, in the first source register by an amount specified in an immediate value or in a control value in a second source register, to generate first and second right-shifted quadwords, the first and second right-shifted quadwords stored in first portions of a temporary register, wherein second portions of the temporary register have values set by the shift circuitry; the execution circuitry to cause selection of 16 most significant bits of the first and second right-shifted quadwords from the first portions of the temporary register to be written to 16 least significant bit regions of first and second quadword data element locations, respectively, of a destination register; and the destination register to store the specified set of the 16 most significant bits of the first and second right-shifted quadwords. ### Claim 2 (depends on 1) The processor of claim 1 wherein the shift circuitry is to insert zeros in bit locations made available by the right-shifting of the first and second quadword data elements. ### Claim 3 (depends on 1) The processor of claim 1 further comprising: rounding and/or saturation circuitry to round and/or saturate values of the first and second right-shifted quadwords prior to storage in the destination register. ### Claim 4 (depends on 3) The processor of claim 3 wherein one or more saturation flags are to be updated responsive to the first and second right-shifted quadwords being saturated. ### Claim 5 (depends on 1) The processor of claim 1 wherein the 16 most significant bits of the first and second right-shifted quadwords comprise all zeroes if the amount specified in the immediate value or in the control value is above a particular number. ### Claim 6 (depends on 1) The processor of claim 1 wherein the immediate value or control value of the second source register comprises a 6-bit value to indicate the shift amount. ### Claim 7 (depends on 1) The processor of claim 1 wherein the first source register and destination register comprise 128-bit packed data registers. ### Claim 8 (depends on 7) The processor of claim 7 wherein the 128-bit packed data registers comprise xmm registers. ### Claim 9 A method comprising: decoding a right-shift instruction to generate a decoded right-shift instruction; storing a plurality of packed quadwords data elements in a first source register; right-shifting at least first and second packed quadword data elements from first and second packed quadword data element locations, respectively, in the first source register by an amount specified in an immediate value or in a control value in a second source register, to generate first and second right-shifted quadwords, the first and second right-shifted quadwords stored in first portions of a temporary register, wherein second portions of the temporary register have values set by shift circuitry; selecting 16 most significant bits of the first and second right-shifted quadwords from the first portions of the temporary register to be written to least significant 16 bit regions of first and second quadword data element locations, respectively, of a destination register; and writing the 16 most significant bits of the first and second right-shifted quadwords to the 16 bit regions of the destination register. ### Claim 10 (depends on 9) The method of claim 9 wherein the shift circuitry is to insert zeros in bit locations made available by the right-shifting of the first and second quadword data elements. ### Claim 11 (depends on 9) The method of claim 9 further comprising: rounding and/or saturating values of the first and second right-shifted quadwords prior to writing to the destination register. ### Claim 12 (depends on 11) The method of claim 11 further comprising: updating one or more saturation flags responsive to the first and second right-shifted quadwords being saturated. ### Claim 13 (depends on 9) The method of claim 9 wherein the 16 most significant bits of the first and second right-shifted quadwords comprise all zeroes if the amount specified in the immediate value or in the control value is above a particular number. ### Claim 14 (depends on 9) The method of claim 9 wherein the immediate value or control value of the second source register comprises a 6-bit value to indicate the shift amount. ### Claim 15 (depends on 9) The method of claim 9 wherein the first source register and destination register comprise 128-bit packed data registers. ### Claim 16 (depends on 15) The method of claim 15 wherein the 128-bit packed data registers comprise xmm registers. ### Claim 17 A non-transitory machine-readable storage medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of: decoding a right-shift instruction to generate a decoded right-shift instruction; storing a plurality of packed quadwords data elements in a first source register; right-shifting at least first and second packed quadword data elements from first and second packed quadword data element locations, respectively, in the first source register by an amount specified in an immediate value or in a control value in a second source register, to generate first and second right-shifted quadwords, the first and second right-shifted quadwords stored in first portions of a temporary register, wherein second portions of the temporary register have values set by shift circuitry; selecting 16 most significant bits of the first and second right-shifted quadwords from the first portions of the temporary register to be written to least significant 16 bit regions of first and second quadword data element locations, respectively, of a destination register; and writing the 16 most significant bits of the first and second right-shifted quadwords to the 16 bit regions of the destination register. ### Claim 18 (depends on 17) The non-transitory machine-readable storage medium of claim 17 wherein the shift circuitry is to insert zeros in bit locations made available by the right-shifting of the first and second quadword data elements. ### Claim 19 (depends on 18) The non-transitory machine-readable storage medium of claim 18 wherein the 16 most significant bits of the first and second right-shifted quadwords comprise all zeroes if the amount specified in the immediate value or in the control value is above a particular number. ### Claim 20 (depends on 17) The non-transitory machine-readable storage medium of claim 17 further comprising: rounding and/or saturating values of the first and second right-shifted quadwords prior to writing to the destination register. ### Claim 21 (depends on 20) The non-transitory machine-readable storage medium of claim 20 further comprising: updating one or more saturation flags responsive to the first and second right-shifted quadwords being saturated. ### Claim 22 (depends on 17) The non-transitory machine-readable storage medium of claim 17 wherein the immediate value or control value of the second source register comprises a 6-bit value to indicate the shift amount. ### Claim 23 (depends on 17) The non-transitory machine-readable storage medium of claim 17 wherein the first source register and destination register comprise 128-bit packed data registers. ### Claim 24 (depends on 23) The non-transitory machine-readable storage medium of claim 23 wherein the 128-bit packed data registers comprise xmm registers.