# US 10,481,881 B2 · Mapping a computer code to wires and gates

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- Number: US 10,481,881 B2
- Document ID: US10481881B2
- Status: Granted
- Kind: B2
- Application number: 15/970,884
- Filed: 2018-05-04
- Published: 2018-12-27
- Granted: 2019-11-19
- Earliest claimed: 2017-06-22
- Assignees: Archeo Futurus, Inc.
- Applicants: Archeo Futurus, Inc.
- Inventors: Daniel Joseph Bentley Kluss
- Web page: https://patentgrep.com/patent/US10481881B2

## CPC

- G06F 8/44: {Encoding}
- G06F 8/35: model driven
- G06F 8/40: Transformation of program code
- G06F 8/443: {Optimisation}
- G06F 9/44: Arrangements for executing specific programs
- G06F 16/00: Information retrieval; Database structures therefor; File system structures therefor
- G06F 30/00: Computer-aided design [CAD]
- G06F 30/343: Logical level
- H03K 19/17704: the logic functions being realised by the interconnection of rows and columns
- G06F 8/4434: {Reducing the memory space required by the program code}
- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F 30/33: Design verification, e.g. functional simulation or model checking
- G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Methods and systems for mapping computer code to wires and gates are disclosed. An example method may include acquiring a code written in a programming language and generating, based on the code, a finite state machine (FSM). The method may further include generating, based on the FSM, a wires and gates representation, the wires and gates representation including a plurality of wires and a plurality of combinatorial logics. The method may further include configuring, based on the wires and gates representation, a field-programmable gate array. Input of each of the plurality of wires may represent a symbol selected from a set of symbols of a structured data packet. The size of the symbol can be equal to a number of bits of the structured data packet transferred per a clock cycle according to a data transmission protocol.

## Claims

### Claim 1

A computer-implemented method for configuring at least one integrated circuit by mapping a computer code to wires and gates, the method comprising:
acquiring a first code, the first code being written in a first language;
parsing, via one or more parsing expression grammar (PEG) modules and based on a first grammar associated with the first language, the first code to convert the first code into a first abstract syntax tree (AST);
converting the first AST into a first non-deterministic finite state machine (NFSM);
converting the first NFSM into a first deterministic finite state machine (DFSM);
optimizing the first DFSM to obtain a second DFSM;
converting, via at least the one or more PEG modules, the second DFSM into a second code, the second code being written in a second language wherein the second code is a translation of the first code;
generating, based on the second DFSM, a wires and gates representation, the wires and gates representation including a plurality of wires and plurality of combinatorial logics; and
configuring, based on the wires and gates representation, at least one integrated circuit.

### Claim 2 (depends on 1)

The method of claim 1, wherein the at least one integrated circuit comprises a field-programmable gate array or an application-specific integrated circuit.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
determining that one or more combinatorial logics of the plurality of combinatorial logics does not depend on input from wires of the plurality of wires; and
in response to the determination, storing the one or more combinatorial logic in a shift register.

### Claim 4 (depends on 2)

The method of claim 2, further comprising:
determining that one or more combinatorial logics of the plurality of combinatorial logics depend on input from wires of the plurality of wires; and
in response to the determination, storing the one or more combinatorial logics in flip-flops.

### Claim 5 (depends on 1)

The method of claim 1, wherein input of each of the plurality of wires represents a symbol from a set of symbols of a structured data packet, a size of the symbol being equal to a number of bits of the structured data packet transferred per clock cycle according to a data transmission protocol.

### Claim 6 (depends on 5)

The method of claim 5, wherein a number of gates and a number of wires in the wires and gates representation is optimized based on a rate of a transferring protocol or a structure of the structured data packet.

### Claim 7 (depends on 5)

The method of claim 5, wherein the structured data packet incudes an ethernet packet, an optical transport network packet, or a peripheral component interconnect express packet.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first language includes a high-level programming language.

### Claim 9 (depends on 1)

The method of claim 1, further comprising optimizing the first DFSM prior to generating the wires and gates representation.

### Claim 10 (depends on 9)

The method of claim 9, wherein optimizing the first DFSM includes minimizing a number of states in a finite state machine.

### Claim 11

A system for configuring at least one integrated circuit by mapping a computer code to wires and gates, the system comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor, the memory storing instructions, which, when executed by the at least one processor, perform a method comprising:
acquiring a first code, the first code being written in a first language;
parsing, via one or more parsing expression grammar (PEG) modules and based on a first grammar associated with the first language, the first code to convert the first code into a first abstract syntax tree (AST);
converting the first AST into a first non-deterministic finite state machine (NFSM);
converting the first NFSM into a first deterministic finite state machine (DFSM);
optimizing the first DFSM to obtain a second DFSM;
converting, via at least the one or more PEG modules, the second DFSM into a second code, the second code being written in a second language wherein the second code is a translation of the first code;
generating, based on the second DFSM, a wires and gates representation, the wires and gates representation including a plurality of wires and a plurality of combinatorial logics; and
configuring, based on the wires and gates representation, an integrated circuit.

### Claim 12 (depends on 11)

The system of claim 11, wherein the at least one integrated circuit comprises a field-programmable gate array or an application-specific integrated circuit.

### Claim 13 (depends on 12)

The system of claim 12, wherein the at least one processor is to:
determine that one or more combinatorial logics of the plurality of combinatorial logics does not depend on input from wires of the plurality of wires; and
in response to the determination, store the one or more combinatorial logic in a shift register.

### Claim 14 (depends on 12)

The system of claim 12, wherein the at least one processor is to:
determine that one or more combinatorial logics of the plurality of combinatorial logics depend on input from wires of the plurality of wires; and
in response to the determination, store the one or more combinatorial logic in flip-flops.

### Claim 15 (depends on 11)

The system of claim 11, wherein an input of each of the plurality of wires represents a symbol selected from a set of symbols of a structured data packet, a size of the symbol being equal to a number of bits of the structured data packet transferred per clock cycle according to a data transmission protocol.

### Claim 16 (depends on 15)

The system of claim 15, wherein a number of gates and a number of wires in the wires and gates representation is optimized based on a rate of a transferring protocol or a structure of the structured data packet.

### Claim 17 (depends on 15)

The system of claim 15, wherein the structured data packet incudes an ethernet packet, an optical transport network packet, or a peripheral component interconnect express packet.

### Claim 18 (depends on 11)

The system of claim 11, wherein the first language is a high-level programming language.

### Claim 19 (depends on 11)

The system of claim 11, wherein the at least one processor is to optimize the first DFSM prior to generating the wires and gates representation.

### Claim 20

A non-transitory computer-readable storage medium having embodied thereon instructions, which, when executed by one or more processors, perform a method for configuring at least one integrated circuit by mapping a computer code to wires and gates, the method comprising:
acquiring a first code, the first code being written in a first language;
parsing, via one or more parsing expression grammar (PEG) modules and based on a first grammar associated with the first language, the first code to convert the first code into a first abstract syntax tree (AST);
converting the first AST into a first non-deterministic finite state machine (NFSM);
converting the first NFSM into a first deterministic finite state machine (DFSM);
optimizing the first DFSM to obtain a second DFSM;
converting, via at least the one or more PEG modules, the second DFSM into a second code, the second code being written in a second language wherein the second code is a translation of the first code;
generating, based on the second DFSM, a wires and gates representation, the wires and gates representation including a plurality of wires and plurality of combinatorial logics; and
configuring, based on the wires and gates representation, at least one integrated circuit.