# US 10,481,869 B1 · Multi-path fused multiply-add with power control > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,481,869 B1 - Document ID: US10481869B1 - Status: Granted - Kind: B1 - Application number: 15/809,648 - Filed: 2017-11-10 - Granted: 2019-11-19 - Earliest claimed: 2017-11-10 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Liang-Kai Wang; Ting Yu; Yu Sun - Web page: https://patentgrep.com/patent/US10481869B1 ## CPC - G06F 7/483: Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} - G06F 7/485: Adding; Subtracting {(G06F7/4833, G06F7/4836 take precedence)} - G06F 7/487: Multiplying; Dividing {(G06F7/4833, G06F7/4836 take precedence)} - G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)} - G06F 9/30014: {with variable precision} - G06F 9/3893: {controlled in tandem, e.g. multiplier-accumulator} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Techniques are disclosed relating to circuitry configured to perform floating-point operations such as fused multiply-addition (FMA) with multiple paths and power control. In some embodiments, an FMA unit includes a near path and multiple far paths and is configured to select a path based on a determined exponent difference. In some embodiments, the FMA unit is configured to operate portions of non-selected paths in a low power state. ## Claims ### Claim 1 An apparatus, comprising: pipelined multiplication circuitry that includes multiple pipeline stages and is configured to generate fused multiply-addition results; classification circuitry configured to classify fused multiply-addition operation based on a difference between an exponent of an addend and a sum of exponents of multiplicands; wherein the multiplication circuitry includes multiple paths and is configured to select paths for performing operations based on the classification, wherein the paths include: near-path circuitry configured to perform operations where the difference is in a first range of values between a first threshold value and a second threshold value; first far-path circuitry configured to perform operations where the difference is in a second range of values that does not overlap with the first range of values; second far-path circuitry configured to perform operations where the difference is in a third range of values that does not overlap with the first or second ranges of values; and third far-path circuitry configured to perform operations where the difference is in a fourth range of values that does not overlap with the first, second, or third ranges of values; wherein the apparatus is configured to, in response to the apparatus assigning a fused multiply-addition operation to the first far-path circuitry using the classification circuitry, operate at least a portion of the near-path circuitry and at least a portion of the second far-path circuitry in a low-power state. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the apparatus is configured to, in response to assigning a fused multiply-addition operation to the first far-path circuitry using the classification circuitry, operate at least a portion of the third far-path circuitry in a low-power state. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the multiplication circuitry is configured to operate on input values with N mantissa bits; wherein the second range of values includes values of the difference smaller than −1; wherein the first range of values includes values of the difference greater than or equal to −1 and smaller than or equal to 2; wherein the third range of values includes values of the difference greater than 2 and smaller than or equal to N+2; and wherein the fourth range of values includes values of the difference greater than N+2. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein, to operate the at least a portion of the near-path circuitry and the at least a portion of the first far-path circuitry in a low-power state, the apparatus is configured to perform one or more of: power gating, clock gating, or data gating. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the near-path circuitry includes leading zero anticipator circuitry and left-shift circuitry. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the near-path circuitry, the first far-path circuitry, and the second far-path circuitry are configured to share mantissa multiplication circuitry and an adder circuit. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the near-path circuitry includes a first rounding circuit, the first far-path circuitry includes a second rounding circuit, and the second far-path circuitry includes a third rounding circuit. ### Claim 8 A non-transitory computer readable storage medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the circuit according to the design, including: pipelined multiplication circuitry that includes multiple pipeline stages and is configured to generate fused multiply-addition results; classification circuitry configured to classify fused multiply-addition operation based on a difference between an exponent of an addend and a sum of exponents of multiplicands; wherein the multiplication circuitry includes multiple paths and is configured to select paths for performing operations based on the classification, wherein the paths include: near-path circuitry configured to perform operations where the difference is in a first range of values between a first threshold value and a second threshold value; first far-path circuitry configured to perform operations where the difference is in a second range of values that does not overlap with the first range of values; second far-path circuitry configured to perform operations where the difference is in a third range of values that does not overlap with the first or second ranges of values; and third far-path circuitry configured to perform operations where the difference is in a fourth range of values that does not overlap with the first, second, or third ranges of values wherein the circuit is configured to, in response to assigning a fused multiply-addition operation to the first far-path circuitry using the classification circuitry, operate at least a portion of the near-path circuitry and at least a portion of the first second far-path circuitry in a low-power state. ### Claim 9 (depends on 8) The non-transitory computer readable storage medium of claim 8, wherein the design information further specifies that the circuit is configured to, in response to assigning a fused multiply-addition operation to the first far-path circuitry using the classification circuitry, operate at least a portion of the third far-path circuitry in a low-power state. ### Claim 10 (depends on 8) The non-transitory computer readable storage medium of claim 8, wherein the design information further specifies that the multiplication circuitry is configured to operate on input values with N mantissa bits; wherein the second range of values includes values of the difference smaller than −1; wherein the first range of values includes values of the difference greater than or equal to −1 and smaller than or equal to 2; wherein the third range of values includes values of the difference greater than 2 and smaller than or equal to N+2; and wherein the fourth range of values includes values of the difference greater than N+2. ### Claim 11 (depends on 8) The non-transitory computer readable storage medium of claim 8, wherein, to operate the at least a portion of the near-path circuitry and the at least a portion of the first far-path circuitry in a low-power state, the circuit is configured to perform one or more of: clock gating, or data gating. ### Claim 12 (depends on 8) The non-transitory computer readable storage medium of claim 8, wherein the near-path circuitry includes leading zero anticipator circuitry and left-shift circuitry. ### Claim 13 (depends on 8) The non-transitory computer readable storage medium of claim 8, wherein the near-path circuitry, the first far-path circuitry, and the second far-path circuitry are configured to share mantissa multiplication circuitry and an adder circuit. ### Claim 14 (depends on 8) The non-transitory computer readable storage medium of claim 8, wherein the near-path circuitry includes a first rounding circuit, the first far-path circuitry includes a second rounding circuit, and the second far-path circuitry includes a third rounding circuit. ### Claim 15 A method, comprising: classifying, by classification circuitry, ones of a plurality of fused multiply-addition operations based on a difference between an exponent of an addend and a sum of exponents of multiplicands; selecting, by control circuitry, ones of multiple paths to perform ones of the plurality of fused multiply-addition operations, including: selecting near-path circuitry in response to the difference being in a first range of values between a first threshold value and a second threshold value; selecting first far-path circuitry in response to the difference being in a second range of values that does not overlap with the first range of values; selecting second far-path circuitry in response to the difference being in a third range of values that does not overlap with the first or second ranges of values; and selecting third far-path circuitry in response to the difference being in a fourth range of values that does not overlap with the first, second, or third ranges of values; and in response to selecting the first far-path circuitry for an operation, operating at least a portion of the near-path circuitry and at least a portion of the first second far-path circuitry in a low-power state. ### Claim 16 (depends on 15) The method of claim 15, further comprising: in response to selecting the first far-path circuitry for an operation, operating at least a portion of the third far-path circuitry in a low-power state. ### Claim 17 (depends on 15) The method of claim 15, wherein the operations have input values with N mantissa bits; wherein the second range of values includes values of the difference smaller than −1; wherein the first range of values includes values of the difference greater than or equal to −1 and smaller than or equal to 2; wherein the third range of values includes values of the difference greater than 2 and smaller than or equal to N+2; and wherein the fourth range of values includes values of the difference greater than N+2. ### Claim 18 (depends on 15) The method of claim 15, wherein the operating the at least a portion of the near path circuitry and the first far path circuitry in a low power state includes data gating. ### Claim 19 (depends on 15) The method of claim 15, wherein the operating the at least a portion of the near path circuitry and the first far path circuitry in a low power state includes clock gating. ### Claim 20 (depends on 15) The method of claim 15, wherein the near-path circuitry uses a leading zero anticipator circuitry and left-shift circuitry.