# US 10,481,815 B2 · MLC based magnetic random access memory used in CNN based digital IC for AI

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- Number: US 10,481,815 B2
- Document ID: US10481815B2
- Status: Granted
- Kind: B2
- Application number: 16/403,678
- Filed: 2019-05-06
- Published: 2019-08-22
- Granted: 2019-11-19
- Earliest claimed: 2017-04-03
- Assignees: Gyrfalcon Technology Inc.
- Applicants: Gyrfalcon Technology Inc.
- Inventors: Chyu-Jiuh Torng; Lin Yang; Qi Dong
- Web page: https://patentgrep.com/patent/US10481815B2

## CPC

- G06F 3/0629: {Configuration or reconfiguration of storage systems}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 13/1668: {Details of memory controller}
- G06F 13/4068: {Electrical coupling}
- G06N 3/045: Combinations of networks
- G06N 3/0464: Convolutional networks [CNN, ConvNet]
- G06N 3/063: using electronic means
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/5607: {using magnetic storage elements}
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/10: Magnetoresistive devices
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

CNN based digital IC for AI contains a number of CNN processing units. Each CNN processing unit contains CNN logic circuits operatively coupling to a memory subsystem. A first subsystem includes an array of first magnetic random access memory (RAM) cells for storing weights and an array of second magnetic RAM cells for storing input signals. A second subsystem includes an array of first magnetic RAM cells for storing one-time-programming weights and an array of second magnetic RAM cells for storing input signals. A third subsystem includes an array of first magnetic RAM cells for storing weights, an array of second magnetic RAM cells for storing input signals and an array of third magnetic RAM cells for storing one-time-programming unique data pattern for security identification. Either MLC STT-RAM or MLC OST-MRAM containing at least two MTJ elements can be configured as different memories for forming memory subsystem.

## Claims

### Claim 1

A digital integrated circuit for artificial intelligence comprising:
a semi-conductor substrate embedded in a single semi-conductor chip, the semi-conductor substrate containing a plurality of cellular neural networks (CNN) processing units, each CNN processing unit comprising:
CNN logic circuits; and
an embedded memory subsystem operatively coupling to the CNN logic circuits;
the embedded memory subsystem further comprising:
an array of first magnetic random access memory cells configured for storing a set of weights; and
an array of second magnetic random access memory cells configured for storing the input signals that require higher endurance of balanced data read and write operations than the array of the first magnetic random access memory cells, each of the first and second magnetic random access memory cells containing at least two vertically stacked magnetic tunnel junction (MTJ) elements.

### Claim 2 (depends on 1)

The digital integrated circuit of claim 1, further comprises at least one input/output data bus operatively coupling to the plurality of the CNN processing units via the memory subsystem and a controller for controlling operations of the plurality of CNN processing units.

### Claim 3 (depends on 2)

The digital integrated circuit of claim 2, wherein said each of the first and second magnetic random access memory cells comprises a multi-level cell spin transfer torque magnetic random access memory (MLC STT-RAM) cell.

### Claim 4 (depends on 2)

The digital integrated circuit of claim 2, wherein said each of the first and second magnetic random access memory cells comprises a multi-level cell orthogonal spin transfer magnetic random access memory (MLC OST-MRAM) cell.

### Claim 5 (depends on 2)

The digital integrated circuit of claim 2, wherein the semi-conductor substrate comprises a silicon substrate.

### Claim 6

A digital integrated circuit for artificial intelligence comprising:
a semi-conductor substrate embedded in a single semi-conductor chip, the semi-conductor substrate containing a plurality of cellular neural networks (CNN) processing units, each CNN processing unit comprising:
CNN logic circuits; and
an embedded memory subsystem operatively coupling to the CNN logic circuits; the embedded memory subsystem further comprising:
an array of first magnetic random access memory cells configured for storing a set of one-time-programming weights; and
an array of second magnetic random access memory cells configured for storing the input signals that require higher endurance of balanced data read and write operations than the array of the first magnetic random access memory cells, each of the first and second magnetic random access memory cells containing at least two vertically stacked magnetic tunnel junction (MTJ) elements.

### Claim 7 (depends on 6)

The digital integrated circuit of claim 6, further comprises at least one input/output data bus operatively coupling to the plurality of the CNN processing units via the memory subsystem and a controller for controlling operations of the plurality of CNN processing units.

### Claim 8 (depends on 7)

The digital integrated circuit of claim 7, wherein the semi-conductor substrate comprises a silicon substrate.

### Claim 9 (depends on 7)

The digital integrated circuit of claim 7, wherein each MTJ element contains an oxide barrier layer.

### Claim 10 (depends on 9)

The digital integrated circuit of claim 9, wherein the set of one-time-programming weights is created by breaking down the oxide barrier layer of the MTJ element by using at least one of following techniques:
(a) applying an electric voltage larger than a voltage range for normal read/write operations;
(b) applying a longer duty cycle of electric current than normal read/write time;
(c) configuring different sizes for the MTJ elements, whereby a smaller size allows easier break-down of the respective oxide barrier layers; and
(d) setting a different gate length of a transistor, whereby a larger transistor allows larger electric current to break down the respective oxide barrier layers.

### Claim 11 (depends on 9)

The digital integrated circuit of claim 9, wherein said each of the first and second magnetic random access memory cells comprises a multi-level cell spin transfer torque magnetic random access memory (MLC STT-RAM) cell.

### Claim 12 (depends on 9)

The digital integrated circuit of claim 9, wherein said each of the first and second magnetic random access memory cells comprises a multi-level cell orthogonal spin transfer magnetic random access memory (MLC OST-MRAM) cell.