# US 10,481,814 B1 · Architecture for asynchronous memory transfer for kernels implemented in integrated circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,481,814 B1 - Document ID: US10481814B1 - Status: Granted - Kind: B1 - Application number: 15/635,646 - Filed: 2017-06-28 - Granted: 2019-11-19 - Earliest claimed: 2017-06-28 - Assignees: Xilinx, Inc. - Applicants: Xilinx, Inc. - Inventors: Heera Nand; Amit Kasat - Web page: https://patentgrep.com/patent/US10481814B1 ## CPC - G06F 3/0629: {Configuration or reconfiguration of storage systems} - G06F 30/27: using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model - G06F 3/0656: {Data buffering arrangements} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0673: {Single storage device} - G06F 30/30: Circuit design - G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Implementing a kernel as circuitry in an integrated circuit can include determining, using a processor, memory access operations and work operations from kernel program code and generating, using the processor, a circuit design from the kernel program code. The circuit design implements a circuit architecture having a memory access circuit configured to perform the memory access operations and an execution circuit configured to perform the work operations concurrently with the memory access operations. ## Claims ### Claim 1 A method for implementing a kernel as circuitry in an integrated circuit, comprising: determining, using a processor, memory access operations and work operations from kernel program code; and generating, using the processor, a circuit design from the kernel program code, wherein the circuit design implements a circuit architecture having a memory access circuit configured to perform the memory access operations and an execution circuit configured to perform the work operations concurrently with the memory access operations. ### Claim 2 (depends on 1) The method of claim 1, wherein the memory access operations comprise read operations and write operations on a global memory. ### Claim 3 (depends on 1) The method of claim 1, wherein the memory access circuit comprises a read channel and a write channel independent of the read channel. ### Claim 4 (depends on 1) The method of claim 1, further comprising: in response to determining a buffer from the kernel program code, generating, within the circuit design, a shared memory, wherein the shared memory is configured to implement the buffer and is accessed by the memory access circuit and the execution circuit. ### Claim 5 (depends on 4) The method of claim 4, wherein the memory access circuit is configured to exchange data between the shared memory and a global memory. ### Claim 6 (depends on 1) The method of claim 1, further comprising: generating, within the circuit design, a read command first-in-first-out memory coupling the execution circuit with the memory access circuit; and generating, within the circuit design, a write command first-in-first-out memory coupling the execution circuit with the memory access circuit. ### Claim 7 (depends on 6) The method of claim 6, wherein the execution circuit is configured to send read commands to the memory access circuit via the read command first-in-first-out memory and write commands to the memory access circuit via the write command first-in-first-out memory. ### Claim 8 (depends on 1) The method of claim 1, further comprising: in response to determining events within the kernel program code, generating a plurality of status registers for the events within the circuit design, wherein the plurality of status registers are accessible by the memory access circuit and the execution circuit, and wherein the plurality of status registers are updated to indicate status of read operations and write operations. ### Claim 9 (depends on 8) The method of claim 8, further comprising: generating, within the circuit design, global status registers indicating status of a read channel and a write channel of the memory access circuit, wherein the global status registers are accessible by the memory access circuit and the execution circuit. ### Claim 10 An integrated circuit having a hardware architecture for a kernel, wherein the hardware architecture comprises: a shared memory circuit configured to implement a buffer of the kernel; a memory access circuit configured to perform memory access operations of the kernel, wherein the memory access operations comprise read operations and write operations that exchange data between a global memory and the shared memory; and an execution circuit coupled to the memory access circuit and configured to perform work operations of the kernel using the data stored in the shared memory. ### Claim 11 (depends on 10) The integrated circuit of claim 10, wherein the hardware architecture includes a number of shared memory circuits corresponding to a number of buffers of the kernel. ### Claim 12 (depends on 10) The integrated circuit of claim 10, wherein the memory access circuit comprises a read channel and a write channel independent of the read channel. ### Claim 13 (depends on 10) The integrated circuit of claim 10, wherein the hardware architecture further comprises: a read command first-in-first-out memory coupling the execution circuit with the memory access circuit; and a write command first-in-first-out memory coupling the execution circuit with the memory access circuit. ### Claim 14 (depends on 13) The integrated circuit of claim 13, wherein the execution circuit is configured to send read commands to the memory access circuit via the read command first-in-first-out memory and write commands to the memory access circuit via the write command first-in-first-out memory. ### Claim 15 (depends on 10) The integrated circuit of claim 10, wherein the hardware architecture further comprises: a plurality of status registers corresponding to events within the kernel, wherein the plurality of status registers are accessible by the memory access circuit and the execution circuit, and wherein the plurality of status registers are updated to indicate status of read operations and write operations. ### Claim 16 (depends on 15) The integrated circuit of claim 15, wherein the hardware architecture further comprises: a plurality of global status registers indicating status of a read channel and a write channel of the memory access circuit, wherein the global status registers are accessible by the memory access circuit and the execution circuit. ### Claim 17 (depends on 10) The integrated circuit of claim 10, wherein the integrated circuit is a programmable integrated circuit. ### Claim 18 A system for implementing a kernel as circuitry in an integrated circuit, comprising: a memory configured to store program code; and a processor coupled to the memory, wherein the processor, in response to executing the program code, is configured to initiate operations including: determining memory access operations and work operations from kernel program code; and generating a circuit design from the kernel program code, wherein the circuit design implements a circuit architecture having a memory access circuit configured to perform the memory access operations and an execution circuit configured to perform the work operations concurrently with the memory access operations. ### Claim 19 (depends on 18) The system of claim 18, wherein the processor is configured to initiate operations further including: in response to determining a buffer from the kernel program code, generating, within the circuit design, a shared memory, wherein the shared memory is configured to implement the buffer and is accessed by the memory access circuit and the execution circuit; generating, within the circuit design, a read command first-in-first-out memory coupling the execution circuit with the memory access circuit; and generating, within the circuit design, a write command first-in-first-out memory coupling the execution circuit with the memory access circuit. ### Claim 20 (depends on 18) The system of claim 18, wherein the processor is configured to initiate operations further including: in response to determining events within the kernel program code, generating a plurality of status registers for the events within the circuit design, wherein the plurality of status registers are accessible by the memory access circuit and the execution circuit, and wherein the plurality of status registers are updated to indicate status of read operations and write operations; and generating, within the circuit design, global status registers indicating status of a read channel and a write channel of the memory access circuit, wherein the global status registers are accessible by the memory access circuit and the execution circuit.