# US 10,481,809 B2 · Read disturb compensation using weighted programming patterns > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,481,809 B2 - Document ID: US10481809B2 - Status: Granted - Kind: B2 - Application number: 15/641,258 - Filed: 2017-07-04 - Published: 2017-10-19 - Granted: 2019-11-19 - Earliest claimed: 2015-09-24 - Assignees: Western Digital Technologies, Inc. - Applicants: Western Digital Technologies, Inc. - Inventors: Abhilash Ravi Kashyap; Dale Charles Main - Web page: https://patentgrep.com/patent/US10481809B2 ## CPC - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 3/0632: {by initialisation or re-initialisation of storage systems} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/10: Programming or data input circuits - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A data storage device includes a solid-state non-volatile memory including a plurality of memory cells and a controller. The controller is configured to reduce a read disturb effect of at least a portion of the solid-state non-volatile memory at least in part by receiving or accessing data to be written to the solid-state non-volatile memory, encoding the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a higher voltage level than the second programming state, and writing the encoded data to the solid-state non-volatile memory. ## Claims ### Claim 1 A data storage device comprising: a solid-state non-volatile memory including a plurality of memory cells; and a controller configured to reduce a read disturb effect of at least a portion of the solid-state non-volatile memory at least in part by: receiving or accessing data to be written to the solid-state non-volatile memory; encoding the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a higher voltage level than the second programming state; and writing the encoded data to the solid-state non-volatile memory. ### Claim 2 (depends on 1) The data storage device of claim 1, further comprising a data randomizer, wherein the controller is further configured to turn off the data randomizer. ### Claim 3 (depends on 1) The data storage device of claim 1, wherein the controller is further configured to: determine that a read disturb programming mode is set; and perform said encoding the data using the programming pattern in response to said determination that the read disturb programming mode is set. ### Claim 4 (depends on 1) The data storage device of claim 1, wherein the controller is further configured to utilize a weighted algorithm when encoding the data using the programming pattern. ### Claim 5 (depends on 1) The data storage device of claim 1, wherein the data to be written is internal system data. ### Claim 6 (depends on 1) The data storage device of claim 1, wherein the controller is further configured to perform said encoding the data using the programming pattern in response to a condition indicating that read disturb compensation is to be implemented. ### Claim 7 (depends on 6) The data storage device of claim 6, wherein the condition corresponds to receipt of a host command to program the data using the programming pattern. ### Claim 8 (depends on 6) The data storage device of claim 6, wherein the condition corresponds to detection of a program/erase cycle preceding high-read utilization of a block of the solid-state non-volatile memory. ### Claim 9 (depends on 1) The data storage device of claim 1, wherein: the controller is further configured to perform said accessing the data at least in part by reading the data from the solid-state non-volatile memory; and when read from the solid-state non-volatile memory, the data is programmed according to a randomized programming pattern. ### Claim 10 (depends on 1) The data storage device of claim 1, wherein second programming state corresponds to a lowest programming state of a multiple-state programming scheme. ### Claim 11 (depends on 1) The data storage device of claim 1, wherein the programming pattern further favors a third programming state over the first programming state, the third programming state being associated with a higher voltage level than the first programming state. ### Claim 12 A data storage device comprising: a solid-state non-volatile memory including a plurality of memory cells; and a controller configured to improve data retention of at least a portion of the solid-state non-volatile memory at least in part by: reading data stored in the solid-state non-volatile memory according to a randomized programming pattern; reencoding the data using a programming pattern that favors a first programming state over a second programming state; and reprogramming the encoded data to the solid-state non-volatile memory. ### Claim 13 (depends on 12) The data storage device of claim 12, wherein the first programming state is associated with a higher voltage level than the second programming state. ### Claim 14 (depends on 12) The data storage device of claim 12, wherein the first programming state is associated with a lower voltage level than the second programming state. ### Claim 15 (depends on 12) The data storage device of claim 12, wherein the controller is further configured to perform said reading, reencoding, and reprogramming in response to a determination that a weighted programming mode is set. ### Claim 16 (depends on 15) The data storage device of claim 15, wherein said determination that the weighted programming mode is set is based on a flag that indicates that the weighted programming mode is set. ### Claim 17 (depends on 12) The data storage device of claim 12, wherein the controller is further configured to perform said reading, reencoding, and reprogramming in anticipation of a power-down of the data storage device. ### Claim 18 A data storage device comprising: a solid-state non-volatile memory including a plurality of memory cells; means for encoding data using a weighted programming pattern that favors a first programming state of a second programming state, the first programming state being associated with a higher voltage level than the second programming state; and controller circuitry configured to reduce a read disturb effect of at least a portion of the solid-state non-volatile memory at least in part by: receiving or accessing data to be written to the solid-state non-volatile memory; encoding the data according to the weighted programming pattern using the means for encoding data; and writing the encoded data to the solid-state non-volatile memory. ### Claim 19 (depends on 18) The data storage device of claim 18, further comprising: a data randomizer; and means for bypassing the data randomizer. ### Claim 20 A method of programming data, the method comprising: receiving or accessing data to be written to a solid-state non-volatile memory; determining that a read disturb compensation programming mode associated with the solid-state non-volatile memory is set; and in response to said determination: encoding the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a higher programming voltage level than the second programming state; and writing the encoded data to the solid-state non-volatile memory. ### Claim 21 (depends on 20) The method of claim 20, further comprising bypassing a data randomizer in response to the determination that the read disturb compensation programming mode is set. ### Claim 22 (depends on 20) The method of claim 20, further comprising receiving a request to set the read disturb compensation programming mode from a host device communicatively coupled to a data storage device over an interface, the data storage device comprising the solid-state non-volatile memory. ### Claim 23 (depends on 20) The method of claim 20, wherein said determining that the read disturb compensation programming mode is set is based on a type of the data. ### Claim 24 (depends on 20) The method of claim 20, wherein the programming pattern further favors a third programming state over the first programming state, the third programming state being associated with a higher voltage level than the first programming state. ### Claim 25 A data storage device comprising: a solid-state non-volatile memory including a plurality of memory cells; and a controller configured to reduce bit error rate for at least a portion of the solid-state non-volatile memory at least in part by: accessing data to be written to the solid-state non-volatile memory; determining that a weighted programming mode is set; and in response to said determining that the weighted programming mode is set: encoding the data using a programming pattern that favors a first programming state over a second programming state; and writing the encoded data to the solid-state non-volatile memory. ### Claim 26 (depends on 25) The data storage device of claim 25, wherein the first programming state is associated with a higher voltage level than the second programming state. ### Claim 27 (depends on 25) The data storage device of claim 25, wherein the first programming state is associated with a lower voltage level than the second programming state.