# US 10,481,795 B2 · Hardware interface component for processing write access requests that identify a register using lesser significant bits of a target address and identify an arithmetic operation to be performed using greater significant bits of the target address

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- Number: US 10,481,795 B2
- Document ID: US10481795B2
- Status: Granted
- Kind: B2
- Application number: 14/708,969
- Filed: 2015-05-11
- Published: 2016-08-11
- Granted: 2019-11-19
- Earliest claimed: 2015-02-10
- Assignees: NXP USA, Inc.
- Applicants: Martin Mienkina; Joseph Charles Circello; Wangsheng Mei; Yan Xiao
- Inventors: Martin Mienkina; Joseph Charles Circello; Wangsheng Mei; Yan Xiao
- Web page: https://patentgrep.com/patent/US10481795B2

## CPC

- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0629: {Configuration or reconfiguration of storage systems}
- G06F 3/0673: {Single storage device}
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/3004: {to perform operations on memory}
- G06F 9/3879: {for non-native instruction execution, e.g. executing a command; for Java instruction set}
- G06F 9/3881: {Arrangements for communication of instructions and data}
- G06F 12/063: {for I/O modules, e.g. memory mapped I/O (I/O protocol G06F13/42)}
- G06F 13/16: for access to memory bus (G06F13/28 takes precedence)
- G06F 13/4068: {Electrical coupling}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A hardware interface component arranged to operably couple at least one arithmetic unit to a an interconnect component of a processing system. The hardware interface component comprises a plurality of program-visible registers and at least one operation decoder component. The at least one operation decoder component is arranged to, upon receipt of a write access request via the interconnect component corresponding to a decorated memory-mapped address range for the hardware interface component, decode a register identifier component of a target address of the received write access request to identify at least one of the program-visible registers, decode a decoration component of the target address of the received write access request to identify an arithmetic operation to be performed, and configure the arithmetic unit to perform the identified arithmetic operation on at least one input operand within the identified at least one program-visible register.

## Claims

### Claim 1

In a processing system having a processor core, an arithmetic unit, and a hardware interface component coupled between the processor core and the arithmetic unit, a method comprising:
receiving, by the hardware interface component, a write access request from the processor core, wherein the write access request has a corresponding target address and write data, and wherein the target address corresponding to the write access address has lesser significant bits and greater significant bits, in which the lesser and greater significant bits do not overlap;
using a lookup table of the hardware interface component to determine whether the target address corresponding to the write access request is within any one of a plurality of memory-mapped address ranges, wherein the plurality of memory- mapped address ranges are non-overlapping and wherein a different arithmetic operation is mapped to each of the plurality of memory-mapped address ranges;
when the target address corresponding to the write access request is determined to be within a first memory-mapped address range of the plurality of memory-mapped address ranges:
using the lesser significant bits of the target address corresponding to the write access request to identify a first input register, wherein the first memory-mapped address range includes the first input register and a result register,
loading the write data into the first input register, wherein the write data is characterized as operand data,
identifying, using the greater significant bits of the target address corresponding to the write access request, a first arithmetic operation to be performed by the arithmetic unit, wherein the first arithmetic operation is mapped to the first memory-mapped address range, and
performing the first arithmetic operation by the arithmetic unit using the operand data in the first input register and loading a result of the first arithmetic operation into the result register.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first arithmetic operation requires N input registers for operand data, in which N is an integer greater than or equal to 1, and the first input register is one of the N input registers, the method further comprising:
storing operand data into the N input registers, except the first input register, prior to receiving the write access request, wherein the first input register is a final input register of the N input registers needing operand data for the first arithmetic operation.

### Claim 3 (depends on 2)

The method of claim 2, wherein the arithmetic unit is triggered to perform the first arithmetic operation after the write data is loaded into the first input register.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
receiving, by the hardware interface component, a read access request from the processor core, wherein the read access request has a corresponding target address, and wherein the target address corresponding to the read access request has lesser significant bits and greater significant bits in which the lesser and greater significant bits of the target address corresponding to the read access request do not overlap;
using the lesser significant bits of the target address corresponding to the read access request to identify an output register, wherein the identified output register is the result register;
using the greater significant bits of the target address corresponding to the read access request to determine if a second arithmetic operation is to be performed; and
when the second arithmetic operation is to be performed, upon valid data being available in the output register, performing the second arithmetic operation on the valid data stored in the output register, wherein the second arithmetic operation is identified by the greater significant bits of the target address corresponding to the read access request.

### Claim 5 (depends on 4)

The method of claim 4, wherein after determining if the second arithmetic operation is to be performed, stalling a bus operation until valid data is available in the output register.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
after performing the second arithmetic operation, stalling the bus operation until valid data is again available in the output register, and transferring the valid data to a data bus.

### Claim 7 (depends on 4)

The method of claim 4, wherein after receiving the read access request, using the lookup table of the hardware interface component to determine that the target address corresponding to the read access request is within one of the plurality of memory-mapped address ranges.

### Claim 8 (depends on 4)

The method of claim 4, further comprising:
when the second arithmetic operation is not to be performed, upon valid data being available in the output register, transferring the valid data to a data bus.

### Claim 9

A processing system, comprising:
a processor core configured to provide a write access request, wherein the write access request has a corresponding target address and write data, and wherein the target address corresponding to the write access address has lesser significant bits and greater significant bits, in which the lesser and greater significant bits do not overlap;
an arithmetic unit; and
a hardware interface component coupled between the processor core and the arithmetic unit and having a lookup table, the hardware interface component configured to:
receive the write access request from the processor core;
use the lookup table of the hardware interface component to determine whether the target address corresponding to the write access request is within any one of a plurality of memory-mapped address ranges, wherein the plurality of memory-mapped address ranges are non-overlapping and wherein a different arithmetic operation is mapped to each of the plurality of memory-mapped address ranges;
when the target address corresponding to the write access request is determined to be within a first memory-mapped address range of the plurality of memory-mapped address ranges:
use the lesser significant bits of the target address corresponding to the write access request to identify a first input register, wherein the first memory-mapped address range includes the first input register and a result register,
load the write data into the first input register, wherein the write data is characterized as operand data,
identify, using the greater significant bits of the target address corresponding to the write access request, a first arithmetic operation to be performed by the arithmetic unit, wherein the first arithmetic operation is mapped to the first memory-mapped address range, and
wherein the arithmetic unit is configured to perform the first arithmetic operation using the operand data in the first input register and loading a result of the first arithmetic operation into the result register.

### Claim 10 (depends on 9)

The processing system of claim 9, wherein the first arithmetic operation requires N input registers for operand data, in which N is an integer greater than or equal to 1, and the first input register is one of the N input registers, and the hardware interface component is further configured to:
store operand data into the N input registers, except the first input register, prior to receiving the write access request, wherein the first input register is a final input register of the N input registers needing operand data for the first arithmetic operation.

### Claim 11 (depends on 10)

The processing system of claim 10, wherein the arithmetic unit is triggered to perform the first arithmetic operation after the write data is loaded into the first input register.

### Claim 12 (depends on 9)

The processing system of claim 9, wherein the hardware interface component is configured to:
receive a read access request from the processor core, wherein the read access request has a corresponding target address, and wherein the target address corresponding to the read access request has lesser significant bits and greater significant bits in which the lesser and greater significant bits of the target address corresponding to the read access request do not overlap;
use the lesser significant bits of the target address corresponding to the read access request to identify an output register, wherein the identified output register is the result register;
use the greater significant bits of the target address corresponding to the read access request to determine if a second arithmetic operation is to be performed; and
wherein:
the arithmetic unit is configured to, when the second arithmetic operation is to be performed and upon valid data being available in the output register, perform the second arithmetic operation on the valid data stored in the output register, wherein the second arithmetic operation is identified by the greater significant bits of the target address corresponding to the read access request.

### Claim 13 (depends on 12)

The processing system of claim 12, wherein after determining if the second arithmetic operation is to be performed, a bus operation is stalled until valid data is available in the output register.

### Claim 14 (depends on 13)

The processing system of claim 13, wherein after performing the second arithmetic operation, the bus operation is stalled until valid data is again available in the output register, and transferring the valid data to a data bus.

### Claim 15 (depends on 12)

The processing system of claim 12, wherein the hardware interface component has a lookup table and is configured to, after receiving the read access request, use the lookup table to determine that the target address corresponding to the read access request is within one of the plurality of memory-mapped address ranges.

### Claim 16 (depends on 12)

The processing system of claim 12, the hardware interface component is further configured to:
when the second arithmetic operation is not to be performed, upon valid data being available in the output register, transfer the valid data to a data bus.