# US 10,481,676 B2 · Systems and methods for frequency mode detection and implementation

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- Number: US 10,481,676 B2
- Document ID: US10481676B2
- Status: Granted
- Kind: B2
- Application number: 16/205,356
- Filed: 2018-11-30
- Published: 2019-04-04
- Granted: 2019-11-19
- Earliest claimed: 2017-08-31
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Kallol Mazumder; Parthasarathy Gajapathy
- Web page: https://patentgrep.com/patent/US10481676B2

## CPC

- G06F 3/002: {Specific input/output arrangements not covered by G06F3/01 - G06F3/16 (other optical apparatus G02B27/00)}
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/1045: {Read-write mode select circuits}
- G11C 7/109: {Control signal input circuits}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G06F 13/1694: {Configuration of memory controller to different memory types}
- G11C 11/4063: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C 2207/2272: Latency related aspects
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The systems and methods provided herein acquire a command over multiple clock cycles and fires it. When a chip select signal (CS) transitions, a first portion of a command address is captured in a first clock cycle after the CS transitions. Then, a second portion of the command address is captured in a second clock cycle immediately after the first clock cycle or in a third clock cycle immediately following the second clock cycle. An internal command is fired, using the first portion of the command address and the second portion of the command address.

## Claims

### Claim 1

A tangible, non-transitory, machine-readable medium, comprising machine-readable instructions, that when executed by one or more processors cause the one or more processors to:
upon a transition of a chip select signal (CS) transition between low and high:
capture a first portion of a command address in a first clock cycle after the transition; and
capture a second portion of the command address in a third clock cycle immediately following a second clock cycle, wherein the second clock cycle immediately follows the first clock cycle;
maintain a toggle indicating when a cycle is a decode cycle;
when the toggle indicates that a cycle immediately previous to a current cycle is a decode cycle, skip command address acquisition during the current cycle; and
fire an internal command, using the first portion of the command address and the second portion of the command address.

### Claim 2 (depends on 1)

The machine-readable medium of claim 1, comprising machine-readable instructions, that when executed by the one or more processors cause the one or more processors to:
when the toggle indicates that a cycle immediately previous to a current cycle is not a decode cycle, perform command address acquisition during the current cycle.

### Claim 3 (depends on 1)

The machine-readable medium of claim 1, comprising machine-readable instructions, that when executed by the one or more processors cause the one or more processors to:
maintain the toggle by alternating the toggle between a high state and a low state for alternating cycles.

### Claim 4 (depends on 1)

The machine-readable medium of claim 1, wherein the CS is constant during the first clock cycle and the second clock cycle.

### Claim 5 (depends on 1)

The machine-readable medium of claim 1, comprising machine-readable instructions, that when executed by the one or more processors cause the one or more processors to:
determine whether a two-cycle command decode indicator is set.

### Claim 6

A tangible, non-transitory, machine-readable medium, comprising machine-readable instructions, that when executed by one or more processors cause the one or more processors to:
upon a transition of a chip select signal (CS) transition between low and high:
capture a first portion of a command address in a first clock cycle after the transition; and
capture a second portion of the command address in a second clock cycle immediately after the first clock cycle; or
capture the second portion of the command address in a third clock cycle immediately following a second clock cycle;
determine whether a two-cycle command decode indicator is set;
when the two-cycle command decode indicator is set, disable decoding in a current cycle; and
fire an internal command, using the first portion of the command address and the second portion of the command address.

### Claim 7 (depends on 6)

The machine-readable medium of claim 6, comprising machine-readable instructions, that when executed by the one or more processors cause the one or more processors to:
when the two-cycle command decode indicator is not set, determine whether a current cycle is a decode cycle.

### Claim 8 (depends on 7)

The machine-readable medium of claim 7, comprising machine-readable instructions, that when executed by the one or more processors cause the one or more processors to:
when the current cycle is a decode cycle, set the two-cycle command decode for a mode-dependent width.

### Claim 9 (depends on 8)

The machine-readable medium of claim 8, comprising machine-readable instructions, that when executed by the one or more processors cause the one or more processors to:
wherein the mode-dependent width comprises one clock cycle when capturing the second portion of the command address in the second clock cycle immediately after the first clock cycle.

### Claim 10 (depends on 8)

The machine-readable medium of claim 8, comprising machine-readable instructions, that when executed by the one or more processors cause the one or more processors to:
wherein the mode-dependent width comprises two clock cycles when capturing the second portion of the command address in the third clock cycle immediately following the second clock cycle.

### Claim 11

A command interface of a memory device, comprising circuitry, configured to:
upon a transition of a chip select signal (CS) between low and high:
capture a first portion of a command address in a first clock cycle after the transition; and
capture a second portion of the command address in a second clock cycle immediately after the first clock cycle; or
capture the second portion of the command address in a third clock cycle immediately following the second clock cycle;
determine whether a two-cycle command decode indicator is set;
when the two-cycle command decode indicator is set, disable decoding in a current cycle; and
fire an internal command, using the first portion of the command address and the second portion of the command address.

### Claim 12 (depends on 11)

The command interface of claim 11, comprising circuitry, configured to:
maintain a toggle indicating when a cycle is a decode cycle.

### Claim 13 (depends on 12)

The command interface of claim 12, comprising circuitry, configured to:
determine, via the toggle, that a cycle previous to a current cycle is a decode cycle; and
based upon the cycle immediately previous to the current cycle being a decode cycle, skip command address acquisition during the current cycle.

### Claim 14 (depends on 12)

The command interface of claim 12, comprising circuitry, configured to:
determine, via the toggle, that a cycle immediately previous to a current cycle is not a decode cycle; and
based upon the cycle immediately previous to the current cycle not being a decode cycle, perform command address acquisition during the current cycle.

### Claim 15 (depends on 11)

The command interface of claim 11, comprising circuitry, configured to:
when the two-cycle command decode indicator is not set:
determine whether a current cycle is a decode cycle; and
when the current cycle is a two-cycle command decode cycle, set the two-cycle command decode for a mode-dependent width;
wherein the mode-dependent width comprises one clock cycle when capturing the second portion of the command address in the second clock cycle immediately after the first clock cycle; and
wherein the mode-dependent width comprises two clock cycles when capturing the second portion of the command address in the third clock cycle immediately after the second clock cycle.

### Claim 16

A method, comprising:
upon a transition of a chip select signal(CS):
capturing a first portion of a command address in a first clock cycle after the transition; and
capturing a second portion of the command address in a second clock cycle immediately after the first clock cycle; or
capturing the second portion of the command address in a third clock cycle immediately following the second clock cycle; and
firing an internal command, using the first portion of the command address and the second portion of the command address.

### Claim 17 (depends on 16)

The method of claim 16, comprising:
determining whether a two-cycle command decode indicator is set; and
when the two-cycle command decode indicator is set, disable decoding in a current cycle.