# US 10,481,668 B2 · System on chip controlling memory power using handshake process and operating method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,481,668 B2 - Document ID: US10481668B2 - Status: Granted - Kind: B2 - Application number: 15/677,050 - Filed: 2017-08-15 - Published: 2018-07-19 - Granted: 2019-11-19 - Earliest claimed: 2017-01-19 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jin-Ook Song; Yun-Ju Kwon; Dong-Sik Cho; Byung-Tak Lee - Web page: https://patentgrep.com/patent/US10481668B2 ## CPC - G06F 1/3225: of memory devices - G06F 1/3275: {Power saving in memory, e.g. RAM, cache} - G06F 1/3287: by switching off individual functional units in the computer system - G06F 1/3296: by lowering the supply or operating voltage - G06F 15/7821: {Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory} - G11C 5/14: Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level. ## Claims ### Claim 1 A system on chip (SoC), comprising: a memory controller configured to control a memory; and a power manager configured to manage a supply power level of the memory, wherein the memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory, and the power manager is configured to adjust the supply power level of the memory according to the memory access level, wherein the power manager is further configured to output, to the memory controller, a result of adjusting the supply power level of the memory. ### Claim 2 (depends on 1) The system on chip of claim 1, wherein the power manager is further configured to determine whether the memory access level is equal to or higher than a preset access level threshold, and when the memory access level is equal to or higher than the preset access level threshold, the power manager is further configured to set the supply power level regarding the memory to a new supply power level that is higher than a current supply power level. ### Claim 3 (depends on 2) The system on chip of claim 2, wherein, after the supply power level of the memory is set, the power manager is further configured to output, to the memory controller, a power increase completion signal regarding the memory. ### Claim 4 (depends on 1) The system on chip of claim 1, wherein the power manager is further configured to determine whether the memory access level is equal to or higher than an access level threshold, and when the memory access level is not equal to or higher than the access level threshold, the power manager is further configured to set the supply power level of the memory to a new supply power level that is lower than a current supply power level. ### Claim 5 (depends on 4) The system on chip of claim 4, wherein the power manager is further configured to output a power decrease request signal to the memory controller before the supply power level of the memory is set to the new supply power level. ### Claim 6 (depends on 4) The system on chip of claim 4, wherein, when the power manager sets the supply power level of the memory to the new supply power level, the memory controller comprises a delaying unit configured to delay outputting a response corresponding to an access of a master or to store the access of the master in an access queue. ### Claim 7 (depends on 4) The system on chip of claim 4, wherein, when the power manager sets the supply power level of the memory to the new supply power level, the memory controller comprises a blocking unit configured to output a fail signal in response to an access of a master. ### Claim 8 (depends on 1) The system on chip of claim 1, wherein the power manager is further configured to adjust the supply power level of the memory by outputting a control signal to the memory. ### Claim 9 (depends on 1) The system on chip of claim 1, wherein the power manager is further configured to adjust the supply power level of the memory by outputting a control signal to a power source that is configured to supply power to the memory. ### Claim 10 A system on chip (SoC), comprising: a memory controller configured to control a memory; and a power manager configured to manage a supply power level of the memory, wherein the memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory, the power manager is configured to adjust the supply power level of the memory according to the memory access level, wherein the memory controller comprises a transition unit configured to inactivate a clock that is input to the memory controller, and the transition unit inactivates the clock occurring during a power transition interval in which the supply power level of the memory is changed. ### Claim 11 A method of operating a power manager comprised in a system on chip (SoC), the method comprising: receiving a memory access level indicating a frequency of accesses to a memory from a memory controller; determining, by the power manager, whether the memory access level is equal to or higher than an access level threshold; and outputting a control signal for setting a supply power level of the memory, wherein, when the power manager determines that the memory access level is equal to or higher than the access level threshold, the outputting of the control signal comprises outputting a control signal for setting the supply power level of the memory to a new supply power level that is higher than a current supply power level, and wherein, when the power manager determines that the memory access level is not equal to or higher than the access level threshold, the method further comprises outputting a power decrease request signal regarding the memory to the memory controller. ### Claim 12 (depends on 11) The method of claim 11, wherein, when the power manager determines that the memory access level is equal to or higher than the access level threshold, the method further comprises outputting a power increase completion signal regarding the memory to the memory controller. ### Claim 13 (depends on 11) The method of claim 11, wherein, when the power manager determines that the memory access level is not equal to or higher than the access level threshold, the method further comprises: receiving an acknowledgement signal from the memory controller, and the outputting of the control signal comprises outputting a control signal for setting the supply power level of the memory to a new supply power level that is lower than a current supply power level. ### Claim 14 (depends on 11) The method of claim 11, wherein the outputting of the control signal comprises: outputting the control signal to a power switch comprised in the memory or to a power source configured to supply power to the memory. ### Claim 15 A system on chip (SoC), comprising: a memory; a processor configured to execute instructions to control the memory; and a power manager configured to manage a supply power level of the memory, wherein, when executed by the processor, the instructions cause the system on chip to perform a process comprising: outputting, from the processor to the power manager, a memory access level indicating a frequency of accesses to the memory, adjusting, by the power manager, the supply power level of the memory according to the memory access level, and either delaying, by the processor, output of a response corresponding to an access of a master, or storing, by the processor, the access of the master in an access queue. ### Claim 16 (depends on 15) The system on chip of claim 15, wherein the process further comprises: comparing, by the power manager, the memory access level to a preset access level threshold, and setting, by the power manager, the supply power level of the memory to a new supply power level based on the comparing. ### Claim 17 (depends on 15) The system on chip of claim 15, wherein the system on chip comprises a single, integrated system with all elements directly or indirectly connected to a single substrate. ### Claim 18 A system on chip (SoC), comprising: a memory; a processor configured to execute instructions to control the memory; and a power manager configured to manage a supply power level of the memory, wherein, when executed by the processor, the instructions cause the system on chip to perform a process comprising: outputting, from the processor to the power manager, a memory access level indicating a frequency of accesses to the memory, adjusting, by the power manager, the supply power level of the memory according to the memory access level, and outputting a fail signal in response to an access of a master.