# US 10,481,626 B1 · Method and apparatus for power distribution using a multiphase voltage regulator with phase redundancy and fault tolerant operation

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- Number: US 10,481,626 B1
- Document ID: US10481626B1
- Status: Granted
- Kind: B1
- Application number: 16/107,528
- Filed: 2018-08-21
- Granted: 2019-11-19
- Earliest claimed: 2018-08-21
- Assignees: Infineon Technologies Austria AG
- Applicants: Infineon Technologies Austria AG
- Inventors: Benjamim Tang; Jinghong Guo; Harrison Hu; Tim Ng; Mattia Oddicini; Herbert Zojer
- Web page: https://patentgrep.com/patent/US10481626B1

## CPC

- H02M 1/32: Means for protecting converters other than automatic disconnection
- G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C)
- H02H 9/045: {adapted to a particular application and not provided for elsewhere}
- H02M 3/1584: {with a plurality of power processing stages connected in parallel}
- G05F 1/463: {Sources providing an output which depends on temperature}
- G05F 1/62: using bucking or boosting DC sources
- H02H 9/02: responsive to excess current {(current limitation for voltage regulators G05F1/573; disconnection after limiting H02H3/025)}
- H02M 1/325: {with means for allowing continuous operation despite a fault, i.e. fault tolerant converters}
- H02M 1/327: {against abnormal temperatures}
- H02M 3/1586: {switched with a phase shift, i.e. interleaved}
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES

## Abstract

A fault-tolerant multiphase voltage regulator includes a plurality of power stages, each of which is configured to deliver a phase current to a processor, and a controller. The controller is configured to: control the plurality of power stages to regulate an output voltage provided to the processor; detect and disable a faulty power stage; generate a throttling signal to indicate if one or more of the power stages is faulty and disabled; and communicate the throttling signal to the processor over a physical line running between the processor and the controller. A corresponding method of operating a fault-tolerant power distribution system is also described.

## Claims

### Claim 1

A fault-tolerant multiphase voltage regulator, comprising:
a plurality of power stages, each of which is configured to deliver a phase current to a processor; and
a controller configured to:
control the plurality of power stages to regulate an output voltage provided to the processor;
detect and disable a faulty power stage;
continue to regulate the output voltage provided to the processor even if one or more power stages of the plurality of power stages is detected as being faulty and disabled;
generate a throttling signal to indicate if one or more of the power stages is faulty and disabled; and
communicate the throttling signal to the processor over a physical line running between the processor and the controller.

### Claim 2 (depends on 1)

The fault-tolerant multiphase voltage regulator of claim 1, wherein the controller is configured to communicate with a system manager independent of communicating with the processor, to indicate to the system manager if one or more power stages of the plurality of power stages is detected as being faulty and disabled.

### Claim 3 (depends on 1)

The fault-tolerant multiphase voltage regulator of claim 1, wherein the controller is configured to generate the throttling signal also in response to an overtemperature condition, so that the throttling signal is generated and communicated to the processor over the same physical line used by the controller to indicate to the processor if any of the following conditions occur:
a power stage is detected as being faulty and disabled; and
an overtemperature condition.

### Claim 4 (depends on 1)

The fault-tolerant multiphase voltage regulator of claim 1, wherein the controller is configured to generate the throttling signal also in response to an overvoltage condition, an undervoltage condition or an overcurrent condition, so that the throttling signal is generated and communicated to the processor over the same physical line used by the controller to indicate to the processor if any of the following conditions occur:
one or more of the plurality of power stages is detected as being faulty and disabled;
the overvoltage condition;
the undervoltage condition; and
the overcurrent condition.

### Claim 5 (depends on 1)

The fault-tolerant multiphase voltage regulator of claim 1, wherein the controller is configured to generate the throttling signal also in response to an overtemperature condition, an overvoltage condition, an undervoltage condition or an overcurrent condition, so that the throttling signal is generated and communicated to the processor over the same physical line used by the controller to indicate to the processor if any of the following conditions occur:
one or more of the plurality of power stages is detected as being faulty and disabled;
the overtemperature condition;
the overvoltage condition;
the undervoltage condition; and
the overcurrent condition.

### Claim 6 (depends on 1)

The fault-tolerant multiphase voltage regulator of claim 1, wherein the controller is configured to place the multiphase voltage regulator in a self-test mode in which the processor is operated at a known computational load and the controller operates each power stage independently to determine if any of the power stages is faulty under the known computational load.

### Claim 7

A method of operating a fault-tolerant multiphase voltage regulator having a plurality of power stages, each of which is configured to deliver a phase current to a processor, the method comprising:
controlling the plurality of power stages to regulate an output voltage provided to the processor;
detecting and disabling a faulty power stage;
continuing to regulate the output voltage provided to the processor even if one or more power stages of the plurality of power stages is detected as being faulty and disabled;
generating a throttling signal to indicate if one or more of the power stages is faulty and disabled; and
communicating the throttling signal to the processor over a physical line running between the processor and the controller.

### Claim 8 (depends on 7)

The method of claim 7, further comprising:
communicating with a system manager independent of communicating with the processor, to indicate to the system manager if one or more power stages of the plurality of power stages is detected as being faulty and disabled.

### Claim 9 (depends on 7)

The method of claim 7, further comprising:
generating the throttling signal also in response to an overtemperature condition, so that the throttling signal is generated and communicated to the processor over the same physical line used to indicate to the processor if any of the following conditions occur:
a power stage is detected as being faulty and disabled; and
an overtemperature condition.

### Claim 10 (depends on 7)

The method of claim 7, further comprising:
generating the throttling signal also in response to an overvoltage condition, an undervoltage condition or an overcurrent condition, so that the throttling signal is generated and communicated to the processor over the same physical line used to indicate to the processor if any of the following conditions occur:
one or more of the plurality of power stages is detected as being faulty and disabled;
the overvoltage condition;
the undervoltage condition; and
the overcurrent condition.

### Claim 11 (depends on 7)

The method of claim 7, further comprising:
generating the throttling signal also in response to an overtemperature condition, an overvoltage condition, an undervoltage condition or an overcurrent condition, so that the throttling signal is generated and communicated to the processor over the same physical line used to indicate to the processor if any of the following conditions occur:
one or more of the plurality of power stages is detected as being faulty and disabled;
the overtemperature condition;
the overvoltage condition;
the undervoltage condition; and
the overcurrent condition.

### Claim 12 (depends on 7)

The method of claim 7, further comprising:
placing the multiphase voltage regulator in a self-test mode in which the processor is operated at a known computational load and each power stage is operated independently to determine if any of the power stages is faulty under the known computational load.

### Claim 13

A fault-tolerant power distribution system, comprising:
a processor;
a multiphase voltage regulator comprising a plurality of power stages, each of which is configured to deliver a phase current to the processor, and a controller configured to:
control the plurality of power stages to regulate an output voltage provided to the processor;
detect and disable a faulty power stage;
continue to regulate the output voltage provided to the processor even if one or more power stages of the plurality of power stages is detected as being faulty and disabled;
generate a throttling signal to indicate if one or more of the power stages is faulty and disabled; and
communicate the throttling signal to the processor over a physical line running between the processor and the controller; and
a system manager in independent communication with the multiphase voltage regulator and the processor.

### Claim 14 (depends on 13)

The fault-tolerant power distribution system of claim 13, wherein the system manager is configured to reduce a computational load of the processor if the controller of the multiphase voltage regulator indicates one or more power stages of the plurality of power stages is detected as being faulty and disabled.

### Claim 15 (depends on 14)

The fault-tolerant power distribution system of claim 14, wherein the system manager is configured to increase the computational load of the processor after the multiphase voltage regulator reports a faulty power stage, shuts down and repowers up again.

### Claim 16 (depends on 14)

The fault-tolerant power distribution system of claim 14, wherein the system manager is configured to direct the multiphase voltage regulator to perform a self-test mode to confirm whether any of the power stages are faulty.

### Claim 17 (depends on 16)

The fault-tolerant power distribution system of claim 16, wherein the system manager is configured to increase the computational load of the processor if the multiphase voltage regulator indicates the self-test mode confirmed none of the power stages are faulty.

### Claim 18 (depends on 16)

The fault-tolerant power distribution system of claim 16, wherein the system manager is configured to shut down the processor and the multiphase voltage regulator if the multiphase voltage regulator indicates the self-test mode confirmed that one or more of the power stages is faulty.

### Claim 19

A method of operating a fault-tolerant power distribution system having a processor, a multiphase voltage regulator comprising a plurality of power stages, each of which is configured to deliver a phase current to the processor, and a system manager in independent communication with the multiphase voltage regulator and the processor, the method comprising:
controlling the plurality of power stages at the multiphase voltage regulator to regulate an output voltage provided to the processor;
detecting and disabling a faulty power stage at the multiphase voltage regulator;
continuing to regulate the output voltage provided to the processor even if one or more power stages of the plurality of power stages is detected as being faulty and disabled;
generating a throttling signal at the multiphase voltage regulator to indicate if one or more of the power stages is faulty and disabled;
communicating the throttling signal from the multiphase voltage regulator to the processor over a physical line running between the processor and the controller; and
managing a computational load of the processor by the system manager based on feedback from the processor and the multiphase voltage regulator.

### Claim 20 (depends on 19)

The method of claim 19, wherein managing the computational load of the processor by the system manager comprises:
reducing the computational load of the processor if the multiphase voltage regulator indicates one or more power stages of the plurality of power stages is detected as being faulty and disabled.

### Claim 21 (depends on 20)

The method of claim 20, further comprising:
increasing, via the system manager, the computational load of the processor after the multiphase voltage regulator reports a faulty power stage, shuts down and repowers up again.

### Claim 22 (depends on 20)

The method of claim 20, further comprising:
directing, via the system manager, the multiphase voltage regulator to perform a self-test mode to confirm whether any of the power stages are faulty.

### Claim 23 (depends on 22)

The method of claim 22, further comprising:
increasing, via the system manager, the computational load of the processor if the multiphase voltage regulator indicates the self-test mode confirmed none of the power stages are faulty.

### Claim 24 (depends on 22)

The method of claim 22, further comprising:
shutting down the processor and the multiphase voltage regulator, via the system manager, if the multiphase voltage regulator indicates the self-test mode confirmed that one or more of the power stages is faulty.
