# US 10,481,444 B2 · Array substrate, display panel and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,481,444 B2 - Document ID: US10481444B2 - Status: Granted - Kind: B2 - Application number: 15/565,775 - Filed: 2017-05-12 - Published: 2019-04-25 - Granted: 2019-11-19 - Earliest claimed: 2016-06-01 - Assignees: Boe Technology Group Co., Ltd. - Applicants: Boe Technology Group Co., Ltd. - Inventors: Jianbo Xian; Hongfei Cheng; Yong Qiao; Yongda Ma - Web page: https://patentgrep.com/patent/US10481444B2 ## CPC - G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]} - G02F 1/1343: Electrodes {(reflective electrodes G02F1/133553)} - G02F 1/136213: {Storage capacitors associated with the pixel electrode} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - G02F 1/133388: {with constructional differences between the display region and the peripheral region} - G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making} - G02F 1/136209: {Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element} - G02F 2201/121: common or background - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The present disclosure provides an array substrate, a display panel and a display device. The array substrate includes a display region and a non-display region surrounding the display region. The array substrate further includes a plurality of gate lines, a plurality of data lines, and a plurality of common electrode lines. The plurality of data lines and the plurality of gate lines define a plurality of pixel units at the display region, and each pixel unit includes a pixel electrode. At least one of the plurality of common electrode lines includes a main line and a branch line located at at least one side of the main line, and at least a part of the branch lines are located at an inner side of a periphery of the display region. ## Claims ### Claim 1 An array substrate, comprising a display region and a non-display region surrounding the display region, wherein the array substrate further comprises a plurality of gate lines, a plurality of data lines, and a plurality of common electrode lines; the plurality of data lines and the plurality of gate lines define a plurality of pixel units at the display region; each pixel unit comprises a pixel electrode; at least one of the plurality of common electrode lines comprises a main line and a branch line located at at least one side of the main line; and at least a part of the branch lines are located at an inner side of a periphery of the display region, wherein the branch line is arranged at two opposite sides of the main line. ### Claim 2 (depends on 1) The array substrate according to claim 1, wherein a portion of the branch line is located at a region where one pixel unit is located, and an orthogonal projection of the branch line onto a plane where the array substrate is located overlaps an orthogonal projection of the pixel electrode of the corresponding pixel unit onto the plane where the array substrate is located. ### Claim 3 (depends on 2) The array substrate according to claim 2, wherein a part of the branch lines are located at a region where a plurality of pixel units are located. ### Claim 4 (depends on 1) The array substrate according to claim 1, wherein each gate line extends in a row direction, two gate lines corresponding to the pixel units in two adjacent rows form a gate line group, each gate line group is arranged between the corresponding pixel units in two adjacent rows, each common electrode line is arranged between two adjacent rows of the pixel units, the gate line groups and the common electrode lines are arranged alternately, and the pixel units in one row are arranged between the gate line group and the common electrode line adjacent to the gate line group; and the branch line comprises a first branch line arranged at one side of the main line and a second branch line arranged at an opposite side of the main line and arranged parallel to, or in a line identical to, the first branch line. ### Claim 5 (depends on 1) The array substrate according to claim 1, wherein the main line is arranged parallel to, and created from a layer identical to, the gate line. ### Claim 6 (depends on 1) The array substrate according to claim 1, wherein the branch line is arranged parallel to the data line. ### Claim 7 (depends on 6) The array substrate according to claim 6, wherein a length of the branch line is ⅗ to 8/9 of a length of the corresponding pixel unit in an extension direction of the data line. ### Claim 8 (depends on 1) The array substrate according to claim 1, wherein a portion of the branch line is located between a first pixel unit and a second pixel unit adjacent to the first pixel unit, and an orthogonal projection of the branch line onto a plane where the array substrate is located overlaps an orthogonal projection of a pixel electrode of the first pixel unit and an orthogonal projection of a pixel electrode of the second pixel unit onto the plane where the array substrate is located. ### Claim 9 (depends on 1) The array substrate according to claim 1, wherein the plurality of common electrode lines comprises a first common electrode line and a second common electrode line arranged opposite to the first common electrode line on the array substrate, a width of each of the first common electrode line and the second common electrode line is greater than a width of each of the other common electrode lines. ### Claim 10 (depends on 1) The array substrate according to claim 1, wherein the common electrode lines comprises a plurality of first common electrode lines and a plurality of second common electrode lines, a width of the first common electrode line is greater than a width of the second common electrode line, and the first common electrode line and the second common electrode line are arranged alternately. ### Claim 11 (depends on 8) The array substrate according to claim 8, wherein the common electrode lines are arranged symmetrically relative to a central axis of the array substrate. ### Claim 12 (depends on 8) The array substrate according to claim 8, wherein at least parts of the common electrode lines are electrically connected to each other at the display region. ### Claim 13 (depends on 8) The array substrate according to claim 8, wherein two adjacent common electrode lines are electrically connected to each other at the display region. ### Claim 14 (depends on 1) A display panel, comprising the array substrate according to claim 1. ### Claim 15 (depends on 14) A display device, comprising the display panel according to claim 14. ### Claim 16 (depends on 2) The array substrate according to claim 2, wherein a portion of the branch line is located between a first pixel unit and a second pixel unit adjacent to the first pixel unit, and an orthogonal projection of the branch line onto the plane where the array substrate is located overlaps an orthogonal projection of a pixel electrode of the first pixel unit and an orthogonal projection of a pixel electrode of the second pixel unit onto the plane where the array substrate is located. ### Claim 17 (depends on 2) The array substrate according to claim 2, wherein the plurality of common electrode lines comprises a first common electrode line and a second common electrode line arranged opposite to the first common electrode line on the array substrate, a width of each of the first common electrode line and the second common electrode line is greater than a width of each of the other common electrode lines. ### Claim 18 (depends on 3) The array substrate according to claim 3, wherein a portion of the branch line is located between a first pixel unit and a second pixel unit adjacent to the first pixel unit, and an orthogonal projection of the branch line onto a plane where the array substrate is located overlaps an orthogonal projection of a pixel electrode of the first pixel unit and an orthogonal projection of a pixel electrode of the second pixel unit onto the plane where the array substrate is located. ### Claim 19 An array substrate, comprising a display region and a non-display region surrounding the display region, wherein the array substrate further comprises a plurality of gate lines, a plurality of data lines, and a plurality of common electrode lines; the plurality of data lines and the plurality of gate lines define a plurality of pixel units at the display region; each pixel unit comprises a pixel electrode; at least one of the plurality of common electrode lines comprises a main line and a branch line located at at least one side of the main line; and at least a part of the branch lines are located at an inner side of a periphery of the display region, wherein the plurality of common electrode lines comprises a first common electrode line and a second common electrode line arranged opposite to the first common electrode line on the array substrate, a width of each of the first common electrode line and the second common electrode line is greater than a width of each of the other common electrode lines. ### Claim 20 An array substrate, comprising a display region and a non-display region surrounding the display region, wherein the array substrate further comprises a plurality of gate lines, a plurality of data lines, and a plurality of common electrode lines; the plurality of data lines and the plurality of gate lines define a plurality of pixel units at the display region; each pixel unit comprises a pixel electrode; at least one of the plurality of common electrode lines comprises a main line and a branch line located at at least one side of the main line; and at least a part of the branch lines are located at an inner side of a periphery of the display region, wherein the common electrode lines comprises a plurality of first common electrode lines and a plurality of second common electrode lines, a width of the first common electrode line is greater than a width of the second common electrode line, and the first common electrode line and the second common electrode line are arranged alternately.