# US 10,481,427 B2 · Array substrate, manufacturing method, display panel and electronic device

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- Number: US 10,481,427 B2
- Document ID: US10481427B2
- Status: Granted
- Kind: B2
- Application number: 15/541,813
- Filed: 2017-01-10
- Published: 2018-04-19
- Granted: 2019-11-19
- Earliest claimed: 2016-04-14
- Assignees: Boe Technology Group Co., Ltd.; Ordos Yuansheng Optoelectronics Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Ordos Yuansheng Optoelectronics Co., Ltd.
- Inventors: Dawei Shi
- Web page: https://patentgrep.com/patent/US10481427B2

## CPC

- G02F 1/133514: {Colour filters}
- G02F 1/13338: {Input devices, e.g. touch panels}
- G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]}
- G02F 1/136209: {Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element}
- G06F 3/0412: {Digitisers structurally integrated in a display}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/134372: {for fringe field switching [FFS] where the common electrode is not patterned}
- G02F 1/136218: {Shield electrodes}
- G06F 2203/04103: Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An array substrate, a manufacturing method, a display panel and an electronic device are provided. The array substrate includes a substrate, and a gate line, an insulation layer, an active layer and a data line which are formed on the substrate. The insulation layer is provided on the gate line, the data line is provided on the gate line through the insulation layer and is crossed with the gate line, and the active layer is provided between the gate line and the data line in a direction perpendicular to the substrate, and a first shield layer is provided on the gate line through the insulation layer, and the first shield layer covers the gate line in the direction perpendicular to the substrate and is electrically insulated from the gate line, the active layer and the data line.

## Claims

### Claim 1

An array substrate, comprising a substrate, and a gate line, an insulation layer, an active layer and a data line which are formed on the substrate,
wherein the insulation layer is provided on the gate line, the data line is provided on the gate line through the insulation layer and is crossed with the gate line, and the active layer is provided between the gate line and the data line in a direction perpendicular to the substrate,
a first shield layer is provided on the gate line through the insulation layer, and the first shield layer covers the gate line in the direction perpendicular to the substrate and is electrically insulated from the gate line, the active layer and the data line,
the array substrate further comprises a common electrode layer provided on a side of the data line away from the gate line, wherein the common electrode layer comprises a plurality of striped common sub-electrodes, and adjacent ones of the striped common sub-electrodes are spaced with an interval,
the first shield layer is configured to be applied with a common voltage, and
the array substrate further comprises a light blocking layer provided between the substrate and the gate line, wherein, the first shield layer is connected to the light blocking layer by a via.

### Claim 2 (depends on 1)

The array substrate of claim 1, wherein the interval extends along a direction the same as a direction along which the gate line extends.

### Claim 3 (depends on 1)

The array substrate of claim 1, wherein at least a portion of the gate line is opposed to the interval in the direction perpendicular to the substrate.

### Claim 4 (depends on 1)

The array substrate of claim 1, wherein the first shield layer is provided in a same layer as the active layer, and the first shield layer is made of a same material as the active layer.

### Claim 5 (depends on 1)

The array substrate of claim 1, wherein the first shield layer is provided in a same layer as the data line, and the first shield layer is made of a same material as the data line.

### Claim 6 (depends on 1)

The array substrate of claim 1, further comprising a second shield layer, wherein, the second shield layer is provided above the gate line and is provided in a different layer from the first shield layer, and the second shield layer covers the gate line in the direction perpendicular to the substrate and is electrically insulated from the gate line, the active layer and the data line.

### Claim 7 (depends on 1)

The array substrate of claim 1, wherein the light blocking layer is made of molybdenum.

### Claim 8 (depends on 1)

A display panel comprising the array substrate of claim 1.

### Claim 9 (depends on 8)

An electronic device, comprising the display panel of claim 8.

### Claim 10

A manufacturing method of an array substrate, the array substrate comprising a substrate and a gate line, an insulation layer, an active layer, a data line provided on the substrate, the manufacturing method comprising:
forming the gate line, the insulation layer, the active layer, and the data line on the substrate in sequence in a direction away from the substrate, and
forming a first shield layer above the gate line through the insulation layer,
wherein the gate line and the data line are crossed with each other,
the first shield layer covers the gate line in a direction perpendicular to the array substrate, and is electrically insulated from the gate line, the active layer and the data line,
the manufacturing method comprises forming a common electrode layer on a side of the data line away from the gate line, dividing the common electrode layer into a plurality of striped common sub-electrodes, so that adjacent ones of the striped common sub-electrodes are spaced with an interval, and
the manufacturing method comprises forming a light blocking layer between the substrate and the gate line, wherein the first shield layer is connected to the light blocking layer by a via.

### Claim 11 (depends on 10)

The method of claim 10, wherein the interval extends along a direction the same as a direction along which the gate line extends.

### Claim 12 (depends on 10)

The method of claim 10, wherein at least a portion of the gate line is opposed to the interval in the direction perpendicular to the array substrate.

### Claim 13 (depends on 10)

The method of claim 10, wherein, the first shield layer is formed simultaneously with forming the active layer, and the first shield layer is made of a same material as the active layer.

### Claim 14 (depends on 10)

The method of claim 10, wherein the first shield layer is formed simultaneously with forming the data line, and the first shield layer is made of a same material as the data line.

### Claim 15 (depends on 10)

The method of claim 10, further comprising forming a second shield layer, wherein the second shield layer is provided above the gate line and is provided in a different layer from the first shield layer, and the second shield layer covers the gate line in the direction perpendicular to the substrate and is electrically insulated from the gate line, the active layer and the data line.