# US 10,481,326 B2 · Photonic chip with an evanescent coupling interface > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,481,326 B2 - Document ID: US10481326B2 - Status: Granted - Kind: B2 - Application number: 15/899,255 - Filed: 2018-02-19 - Published: 2018-07-05 - Granted: 2019-11-19 - Earliest claimed: 2015-11-13 - Assignees: Cisco Technology, Inc. - Applicants: Cisco Technology, Inc. - Inventors: Vipulkumar Patel; Mark Webster; Ravi Tummidi; Mary Nadeau - Web page: https://patentgrep.com/patent/US10481326B2 ## CPC - G02B 6/12004: {Combinations of two or more optical elements} - G02B 6/12002: {Three-dimensional structures} - G02B 6/125: Bends, branchings or intersections - G02B 6/305: {and having an integrated mode-size expanding section, e.g. tapered waveguide} - G02B 6/34: utilising prism or grating {(G02B6/293 takes precedence)} - G02B 6/4206: {Optical features (G02B6/4207, G02B6/421 take precedence)} - G02B 6/4274: {Electrical aspects (G02B6/4263 and G02B6/4265 take precedence)} - G02B 6/4291: {by accessing the evanescent field of the light guide} - G02B 6/1228: {Tapered waveguides, e.g. integrated spot-size transformers (for coupling with fibres G02B6/305)} - G02B 6/124: Geodesic lenses or integrated gratings - G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS ## Abstract Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate. ## Claims ### Claim 1 An optical system, comprising: a photonic chip, comprising: a silicon waveguide, an active surface layer comprising a first optical component optically coupled to the silicon waveguide, and an evanescent coupler spaced apart from the silicon waveguide along a direction normal to the active surface layer, wherein the evanescent coupler is optically coupled to the silicon waveguide; and an external optical device, comprising: a second optical component, a spot size converter coupled to the second optical component and overlapping the evanescent coupler, wherein the spot size converter is configured to alter a mode size of optical signals transferred between the evanescent coupler and the spot size converter, and wherein the photonic chip and the external optical device are bonded together along a coupling interface that is parallel to the active surface layer. ### Claim 2 (depends on 1) The optical system of claim 1, wherein the photonic chip further comprises: an optical via disposed between the evanescent coupler and the silicon waveguide, wherein the optical via includes a plurality of waveguides disposed at different layers spaced apart along the direction normal to the active surface layer, and wherein portions of the plurality of waveguides are tapered to transfer optical signals between the evanescent coupler and the silicon waveguide. ### Claim 3 (depends on 2) The optical system of claim 2, wherein the photonic chip further comprises: a plurality of metal and via routing layers coupled to the first optical component, wherein the plurality of waveguides of the optical via are disposed on at least some of the plurality of metal and via routing layers. ### Claim 4 (depends on 1) The optical system of claim 1, wherein the evanescent coupler is disposed on a first side of an insulation layer that is opposite a second side of the insulation layer that contacts the active surface layer, wherein a second end of the evanescent coupler overlaps a first end of the silicon waveguide along the direction normal to the insulation layer and the active surface layer, and wherein the second end of the evanescent coupler is inversely tapered relative to the first end of the silicon waveguide such that the evanescent coupler and the silicon waveguide are evanescently coupled. ### Claim 5 (depends on 4) The optical system of claim 4, wherein the coupling interface and the external optical device are disposed on a first side of the active surface layer, wherein the photonic chip further comprises: a through oxide via extending from the coupling interface, through the insulation layer, and through the active surface layer to connect to at least one metal layer coupled to the first optical component. ### Claim 6 (depends on 1) The optical system of claim 1, further comprising: a coupling waveguide in the spot size converter, wherein a width of a first end of the coupling waveguide decreases as the coupling waveguide extends along a first direction and a width of a first end of the evanescent coupler increases as the evanescent coupler extends along the first direction, thereby creating an inverse taper. ### Claim 7 (depends on 6) The optical system of claim 6, wherein a gap between the first ends of the coupling waveguide and the evanescent coupler along the direction normal to the active surface layer is less than or equal to 500 nanometers. ### Claim 8 (depends on 1) The optical system of claim 1, wherein the external optical device is bonded to the photonic chip at the coupling interface using at least one of an oxide-oxide bond, a solder collapse bond, and an epoxy collapse bond. ### Claim 9 (depends on 1) The optical system of claim 1, wherein the second optical component is a light source configured to transmit light into the silicon waveguide through the spot size converter and evanescent coupler. ### Claim 10 A photonic chip, comprising: an active surface layer comprising a first optical component optically coupled to a silicon waveguide; an evanescent coupler spaced apart from the silicon waveguide along a direction normal to the active surface layer, wherein the evanescent coupler is optically coupled to the silicon waveguide; an optical via disposed between the evanescent coupler and the silicon waveguide, wherein the optical via includes a plurality of waveguides disposed at different layers spaced apart along the direction normal to the active surface layer, and wherein portions of the plurality of waveguides are tapered to transfer optical signals between the evanescent coupler and the silicon waveguide; and a coupling interface parallel to the active surface layer, wherein the evanescent coupler is arranged proximate to the coupling interface to permit the evanescent coupler to optically couple to an external optical device when the external optical device is bonded to the coupling interface. ### Claim 11 (depends on 10) The photonic chip of claim 10, further comprising: a plurality of metal and via routing layers coupled to the first optical component, wherein the plurality of waveguides of the optical via are disposed on at least some of the plurality of metal and via routing layers. ### Claim 12 (depends on 10) The photonic chip of claim 10, further comprising: a coupling waveguide, wherein a width of a first end of the silicon waveguide decreases as the silicon waveguide extends along a first direction and a width of a first end of the evanescent coupler increases as the evanescent coupler extends along the first direction thereby creating an inverse taper. ### Claim 13 A method, comprising: providing a photonic chip comprising an insulation layer, an active surface layer contacting the insulation layer, and a plurality of metal routing layers electrically coupled to a first optical component in the active surface layer, and wherein the first optical component is optically coupled to a silicon waveguide; bonding an oxide layer in a wafer to the photonic chip; and disposing an evanescent coupler on the insulation layer, wherein the evanescent coupler is optically coupled to the silicon waveguide in the active surface layer. ### Claim 14 (depends on 13) The method of claim 13, further comprising: disposing an insulative material over the evanescent coupler; and mounting an external optical device on the insulative material, the external optical device comprising a spot size converter evanescently coupled to the evanescent coupler and a second optical component coupled to the spot size converter, wherein the spot size converter is configured to alter a mode size of optical signals transferred between the silicon waveguide and the second optical component. ### Claim 15 (depends on 13) The method of claim 13, wherein the wafer comprises CMOS logic disposed in a semiconductor substrate and a plurality of metal routing layers in the oxide layer, wherein the plurality of metal routing layers are electrically coupled to the CMOS logic. ### Claim 16 (depends on 15) The method of claim 15, further comprising: forming a through oxide via extending through the insulation layer, through the active surface layer, and coupling to one of the plurality of metal routing layers. ### Claim 17 (depends on 16) The method of claim 16, wherein the through oxide via extends through a first side of the oxide layer and electrically connects to one of the plurality of metal routing layers in the wafer. ### Claim 18 A photonic chip, comprising: an active surface layer comprising a first optical component optically coupled to a silicon waveguide; an evanescent coupler spaced apart from the silicon waveguide along a direction normal to the active surface layer, wherein the evanescent coupler is optically coupled to the silicon waveguide, and wherein the evanescent coupler is disposed on a first side of an insulation layer that is opposite a second side of the insulation layer that contacts the active surface layer, wherein a second end of the evanescent coupler overlaps a first end of the silicon waveguide along the direction normal to the insulation layer and the active surface layer, and wherein the second end of the evanescent coupler is inversely tapered relative to the first end of the silicon waveguide such that the evanescent coupler and the silicon waveguide are evanescently coupled; and a coupling interface parallel to the active surface layer, wherein the evanescent coupler is arranged proximate to the coupling interface to permit the evanescent coupler to optically couple to an external optical device when the external optical device is bonded to the coupling interface. ### Claim 19 (depends on 18) The photonic chip of claim 18, wherein the coupling interface is disposed on the first side of the insulation layer, wherein the photonic chip further comprises: a through oxide via extending from the coupling interface, through the insulation layer, and through the active surface layer to connect to at least one metal layer coupled to the first optical component.