# US 10,481,219 B2 · Magnetic field sensor with feedback loop for test signal processing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,481,219 B2 - Document ID: US10481219B2 - Status: Granted - Kind: B2 - Application number: 15/897,708 - Filed: 2018-02-15 - Published: 2019-03-14 - Granted: 2019-11-19 - Earliest claimed: 2017-09-11 - Assignees: Allegro MicroSystems, LLC - Applicants: Allegro MicroSystems, LLC - Inventors: Hernán D. Romero; Octavio H. Alpago - Web page: https://patentgrep.com/patent/US10481219B2 ## CPC - G01R 33/075: {Hall devices configured for spinning current measurements} - H03F 1/26: Modifications of amplifiers to reduce influence of noise generated by amplifying elements - H03F 3/387: with semiconductor devices only - H03F 3/45475: {using IC blocks as the active amplifying circuit} - H03F 3/45977: {using switching means, e.g. sample and hold} - H03M 1/00: Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) - H10N 52/80: Constructional details - H03F 2200/331: Sigma delta modulation being used in an amplifying circuit - H03F 2200/408: the output amplifying stage of an amplifier comprising three power stages - H03F 2203/45528: the FBC comprising one or more passive resistors and being coupled between the LC and the IC - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H03F: AMPLIFIERS - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract A sensor circuit may include one or more feedback loops to process and attenuate ripple and/or a test signal. The sensor circuit may comprise at least one magnetic field sensing element to generate a magnetic field signal representing a magnetic field to be measured, a test signal generator circuit configured to generate a test signal and combine the test signal with the magnetic field signal to generate a combined signal, and a signal path for processing the combined signal. The signal path may comprise an amplifier circuit to amplify the combined signal, an analog-to-digital converter (ADC) to convert the combined signal to a digital combined signal, and a feedback circuitry coupled to receive the digital combined signal and extract the test signal. A test comparator circuit compares the extracted test signal to a reference signal. ## Claims ### Claim 1 A sensor circuit comprising: at least one magnetic field sensing element to generate a magnetic field signal representing a magnetic field to be measured; a test signal generator circuit configured to generate a test signal and combine the test signal with the magnetic field signal to generate a combined signal; a signal path for processing the combined signal, the signal path comprising: an amplifier circuit to amplify the combined signal; an analog-to-digital converter (ADC) to convert the combined signal to a digital combined signal; a feedback circuit coupled to receive the digital signal and extract the test signal; and a test comparator circuit to compare the extracted test signal to a reference signal. ### Claim 2 (depends on 1) The sensor circuit of claim 1 wherein the amplifier circuit is a chopper-stabilized amplifier circuit configured to receive and amplify the combined signal. ### Claim 3 (depends on 1) The sensor circuit of claim 1 wherein the (ADC) comprises a sigma-delta modulator (SDM). ### Claim 4 (depends on 1) The sensor circuit of claim 1 wherein the feedback circuit comprises a demodulator circuit to extract the test signal from the digital combined signal by inverting a bit stream of the digital combined signal from the ADC according to a test signal frequency rate. ### Claim 5 (depends on 1) The sensor circuit of claim 1 wherein the feedback circuit comprises a feedback circuit amplifier to amplify the extracted test signal. ### Claim 6 (depends on 5) The sensor signal of claim 5 wherein the feedback amplifier circuit amplifies the extracted test signal. ### Claim 7 (depends on 1) The sensor circuit of claim 1 wherein the feedback circuit comprises a digital-to-analog converter (DAC) to convert the extracted test signal to an analog extracted test signal. ### Claim 8 (depends on 7) The sensor circuit of claim 7 wherein the DAC is coupled to the signal path to feed the extracted test signal back into the signal path to reduce an amplitude of a portion of the digital combined signal attributed to the test signal. ### Claim 9 (depends on 7) The sensor circuit of claim 7 wherein the DAC is a current-steering DAC. ### Claim 10 (depends on 1) The sensor circuit of claim 1 wherein the feedback circuit comprises a digital integrator to integrate the test signal. ### Claim 11 (depends on 2) The sensor circuit of claim 2 wherein the signal path further comprises a second feedback circuit configured to reduce a ripple in a signal generated by the amplifier circuit. ### Claim 12 (depends on 1) The sensor circuit of claim 1 wherein the comparator circuit generates an error if the value of the extracted test signal falls outside a predetermined threshold. ### Claim 13 (depends on 11) The sensor circuit of claim 11 wherein the second feedback circuit comprises: a demodulator to demodulate a signal from the ADC in a digital domain by inverting a bit stream of the signal from the ADC according to a frequency chopping rate; a digital integrator configured to integrate an output signal of the demodulator to form an integrated signal; and a digital-to-analog converter (DAC) configured to convert the integrated signal to an analog signal and provide the analog signal to the chopper-stabilized amplifier circuit. ### Claim 14 (depends on 1) The sensor circuit of claim 1 further comprising a decimation filter coupled to an output of the ADC, wherein the feedback circuit is coupled to an output of the decimation filter, and wherein the decimation filter comprises at least one notch filter to reduce an amplitude of a portion of the digital combined signal attributed to noise. ### Claim 15 (depends on 14) The sensor circuit of claim 14 wherein the first decimation filter uses a first decimation rate with a frequency that is twice the frequency of the test signal or higher. ### Claim 16 (depends on 14) The sensor circuit of claim 14 further comprising a second decimation filter coupled to an output of the first decimation filter. ### Claim 17 (depends on 16) The sensor circuit of claim 16, wherein the second decimation filter is configured to adjust a bandwidth of a forward signal path of the sensor circuit. ### Claim 18 (depends on 1) The sensor circuit of claim 1 wherein the feedback circuit comprises a decimation filter coupled to filter noise and pass the extracted test signal. ### Claim 19 (depends on 1) The sensor circuit of claim 1 wherein the reference signal has an amplitude of about zero. ### Claim 20 (depends on 2) The sensor circuit of claim 2, wherein the chopper-stabilized amplifier circuit comprises: a first switch to receive signals from the at least one magnetic sensing element; a first amplifier configured to receive signals from the first switch; a second switch configured to receive signals from the first amplifier; a second amplifier configured to receive signals from the second switch; a third switch configured to receive signals from the second amplifier; and a third amplifier configured to receive signals from the third switch. ### Claim 21 (depends on 1) The sensor circuit of claim 1 wherein the at least one magnetic sensing element comprises at least one of: a Hall effect element, a magnetoresistance element, or a magnetotransistor. ### Claim 22 (depends on 21) The sensor circuit of claim 21 wherein the at least one Hall effect element comprises one or more of a planar Hall element, a vertical Hall element or a Circular Vertical Hall (CVH) element. ### Claim 23 (depends on 21) The sensor circuit of claim 21 wherein the magnetoresistive element is chosen from the list consisting of: a giant magnetoresistance (GMR) element, an anisotropic magnetoresistance element (AMR), a tunneling magnetoresistance (TMR) element, and a magnetic tunnel junction (MTJ).