# US 10,481,205 B2 · Robust secure testing of integrated circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,481,205 B2 - Document ID: US10481205B2 - Status: Granted - Kind: B2 - Application number: 15/704,515 - Filed: 2017-09-14 - Published: 2019-01-31 - Granted: 2019-11-19 - Earliest claimed: 2017-07-27 - Assignees: Seagate Technology LLC - Applicants: Seagate Technology LLC - Inventors: Rajesh Maruti Bhagwat; Jackson Ellis; Mark von Gnechten - Web page: https://patentgrep.com/patent/US10481205B2 ## CPC - G01R 31/318544: {Scanning methods, algorithms and patterns (G01R31/3183 takes precedence)} - G01R 31/2851: {Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801)} - G01R 31/31701: {Arrangements for setting the Unit Under Test [UUT] in a test mode} - G01R 31/318588: {Security aspects} - G06F 9/30079: {Pipeline control instructions, e.g. multicycle NOP} - G06F 12/1425: {the protection being physical, e.g. cell, word, block} - G06F 12/1433: {for a module or a part of a module} - G06F 21/72: in cryptographic circuits - G06F 2212/1052: Security improvement - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method includes configuring a first set of blocks of a plurality of blocks of an IC chip as secure data blocks, and configuring a second set of blocks of the plurality of blocks as non-secure data blocks. The method further includes receiving a test mode entry request in the IC chip. In response to the IC chip receiving the test mode entry request, carrying out a data-initialization operation on the plurality of blocks independently of whether any blocks of the plurality of blocks are configured as the secure data blocks or the non-secure data blocks. An IC chip data output is disabled during the data-initialization operation. ## Claims ### Claim 1 A method comprising: providing an integrated circuit (IC) chip having a plurality of blocks; configuring a first set of blocks of the plurality of blocks of the IC chip as secure data blocks, with at least one of the secure data blocks comprising a memory; configuring a second set of blocks of the plurality of blocks of the IC chip as non-secure data blocks; receiving a test mode entry request in the IC chip; in response to the IC chip receiving the test mode entry request, carrying out a data-initialization operation on the plurality of blocks independently of whether any blocks of the plurality of blocks are configured as the secure data blocks or the non-secure data blocks, the data-initialization operation including writing a predetermined data pattern into the memory to initialize the memory; and disabling an IC chip data output during the data-initialization operation. ### Claim 2 (depends on 1) The method of claim 1 and further comprising, as part of the data-initialization operation, reading a portion of the predetermined data pattern from the memory into a pipeline register coupled to the memory, thereby flushing the pipeline register. ### Claim 3 (depends on 1) The method of claim 1 and wherein the plurality of data blocks comprises a plurality of scan chains, and wherein each of the plurality of scan chains comprises a plurality of flip-flops, and wherein carrying out the data-initialization operation comprises shifting a predetermined data pattern into all of the plurality of flip-flops in all of the plurality of scan chains. ### Claim 4 (depends on 1) The method of claim 1 and wherein the test mode entry request is a direct test mode entry request. ### Claim 5 (depends on 1) The method of claim 1 and wherein the test mode entry request is an indirect test mode entry request from a functional mode of the IC chip. ### Claim 6 (depends on 5) The method of claim 5 and wherein the functional mode is a safe mode that is implemented by setting a fuse bit. ### Claim 7 (depends on 6) The method of claim 6 and wherein, if the fuse bit is set, carrying the out a reset of the IC chip and carrying out the data-initialization operation. ### Claim 8 (depends on 6) The method of claim 6 and further comprising providing a firmware override that enables bypassing the data-initialization operation to read data from the IC chip. ### Claim 9 (depends on 6) The method of claim 6 and further comprising providing a bypass feature that provides access to data in to IC chip without carrying out the data initialization operation if the fuse bit is not set. ### Claim 10 An integrated circuit (IC) chip comprising: a plurality of blocks in which some blocks are configured to store secure data and other blocks are configured to store non-secure data, the plurality of data blocks comprises a plurality of scan chains, with each of the plurality of scan chains comprising a plurality of flip-flops and at least one of the plurality of scan chains including at least one flip-flop without a reset pin in the plurality flip-flops; and a scan security module configured to: in response to the IC chip receiving a test mode entry request, carry out a data-initialization operation on the plurality of blocks independently of whether any blocks of the plurality of blocks are configured to store the secure data or the non-secure data; shift a predetermined data pattern into the at last one flip-flop without the reset pin as part of the data-initialization operation; and disable an IC chip data output during the data-initialization operation. ### Claim 11 (depends on 10) The IC chip of claim 10 and wherein at least one of the plurality of blocks comprises a memory, and wherein the scan security module is configured to initiate an operation to write a predetermined data pattern into the memory as part of the data-initialization operation. ### Claim 12 (depends on 10) The IC chip of claim 10 and further comprising a pipeline register coupled to the memory, and wherein the scan security module is further configured to read a portion of the predetermined data pattern from the memory into the pipeline register coupled to the memory. ### Claim 13 A method comprising: providing an IC chip having a plurality of scan chains and at least one memory; receiving a test mode entry request in the IC chip having the plurality of scan chains and the at least one memory; and in response to the IC chip receiving the test mode entry request, carrying out a data-initialization operation on the plurality of scan chains and the at least one memory, the data initialization operation including writing a first predetermined data pattern into the at least one memory to initialize the at least one memory, and reading a portion of the predetermined data pattern from the at least one memory into a pipeline register coupled to the at least one memory, thereby flushing the pipeline register. ### Claim 14 (depends on 13) The method of claim 13 and further comprising disabling an output of the IC chip during the data-initialization operation. ### Claim 15 (depends on 13) The method of claim 13 and wherein each of the plurality of scan chains comprises a plurality of flip-flops, and wherein carrying out the data-initialization operation comprises shifting a second predetermined data pattern into all of the plurality of flip-flops in all of the plurality of scan chains. ### Claim 16 (depends on 13) The method of claim 13 and wherein the test mode entry request is a direct test mode entry request. ### Claim 17 (depends on 13) The method of claim 13 and wherein the test mode entry request is an indirect test mode entry request from a functional mode of the IC chip. ### Claim 18 (depends on 17) The method of claim 17 and wherein the functional mode is a safe mode that is implemented by setting a fuse bit.