# US 10,481,204 B2 · Methods and systems to measure a signal on an integrated circuit die > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,481,204 B2 - Document ID: US10481204B2 - Status: Granted - Kind: B2 - Application number: 14/508,082 - Filed: 2014-10-07 - Published: 2015-01-22 - Granted: 2019-11-19 - Earliest claimed: 2010-12-24 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Vinu K. Elias - Web page: https://patentgrep.com/patent/US10481204B2 ## CPC - G01R 31/3183: Generation of test inputs, e.g. test vectors, patterns or sequences - G01R 31/2851: {Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801)} - G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract Methods and systems to measure a signal on an integrated circuit die. An on-die measurement circuit may measure an on-die signal relative to an off-die generated reference signal, which may include a series of increasing voltage steps. The on-die measurement circuit may continuously compare voltages of the on-die signal and the off-die generated reference signal, and may generate an indication when the off-die reference signal exceeds the on-die signal. The measurement circuit may generate the indication from a voltage source other than the on-die signal to be measured, and/or may generate the indication with a relatively large voltage swing. The indication may be output off-die for evaluation, such as for testing, debugging, characterization, and/or operational monitoring. A unity gain analog buffer may be provided to tap the on-die signal proximate to a node of interest, which may be implemented within the on-die measurement circuit. ## Claims ### Claim 1 A processor comprising: a first pad; a second pad; and a measurement circuit having: a first input node to receive a test signal; a second input node to receive an adjustable reference signal from the first pad; and an output node to provide an indication of a relation between the test signal and the reference signal to the second pad, wherein the measurement circuit is to protect the first input node from the second pad to preserve signal fidelity of the test signal; and a multiplexer coupled to the measurement circuit, wherein the multiplexer is to selectively provide an output from multiple measurement circuits including the measurement circuit. ### Claim 2 (depends on 1) The processor of claim 1, wherein the test signal is to be provided from a circuit having a different power supply than the measurement circuit. ### Claim 3 (depends on 1) The processor of claim 1, including a test circuit to be tested is to generate the test signal and is to operate on a first power supply. ### Claim 4 (depends on 3) The processor of claim 3, wherein the measurement circuit has a circuitry to operate at a second power supply higher than the first power supply. ### Claim 5 (depends on 4) The processor of claim 4, wherein the indication is to be generated by the circuitry, which is to operate on the second power supply. ### Claim 6 (depends on 1) The processor of claim 1, wherein the measurement circuit is a first measurement circuit, and wherein the multiplexer includes: a first input coupled to the output node of the first measurement circuit; a second input coupled to an output of a second measurement circuit; and an output coupled to the second pad. ### Claim 7 (depends on 6) The processor of claim 6, wherein the test signal is a first test signal, and wherein the second measurement circuit has an input to receive second test signal. ### Claim 8 (depends on 1) The processor of claim 1, wherein the measurement circuit comprises a comparator having at least two inputs coupled to the first and second inputs respectively. ### Claim 9 (depends on 8) The processor of claim 8, wherein the comparator comprises an output node to provide a digital signal. ### Claim 10 (depends on 8) The processor of claim 8, wherein the comparator is to change state of its output when voltage of the test signal is higher than voltage of the reference signal. ### Claim 11 (depends on 1) The processor of claim 1, wherein the reference signal is generated by an off-chip source. ### Claim 12 (depends on 6) The processor of claim 6, wherein the off-chip source is to provide an adjustable voltage threshold as the adjustable reference signal. ### Claim 13 (depends on 1) The processor of claim 1 comprising a circuit to provide an analog signal as the test signal. ### Claim 14 An integrated circuit apparatus, comprising: a test circuit to be tested, to operate on and powered by a first power supply voltage, wherein the test circuit is to provide a test signal; a first pad; a second pad; and a measurement circuit having circuitry to operate at and powered by a second power supply voltage higher than the first power supply voltage, the measurement circuit including: a first input node to receive the test signal; a second input node to receive a reference signal from the first pad; and an output node to provide an indication signal, indicative of a relation between the test signal and the reference signal, to the second pad, wherein the indication signal is to be generated by the circuitry which is to operate on the second power supply voltage, wherein the measurement circuit is one of a plurality of different measurement circuits whose outputs are selectably coupled through one or more multiplexers to measure a selected one of a plurality of different test signals. ### Claim 15 (depends on 14) The integrated circuit apparatus of claim 14, wherein the measurement circuit includes a comparator. ### Claim 16 (depends on 14) The integrated circuit apparatus of claim 14, wherein the reference signal is generated by an off-chip source. ### Claim 17 (depends on 16) The integrated circuit apparatus of claim 16, wherein the off-chip source is to provide an adjustable voltage threshold as the reference signal.