# US 10,481,202 B2 · In-field self-test controller for safety critical automotive use cases

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- Number: US 10,481,202 B2
- Document ID: US10481202B2
- Status: Granted
- Kind: B2
- Application number: 15/835,227
- Filed: 2017-12-07
- Published: 2018-08-16
- Granted: 2019-11-19
- Earliest claimed: 2017-02-13
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Arvind Jain; Nishi Bhushan Singh; Rahul Gulati; Pranjal Bhuyan; Rakesh Kumar Kinger; Roberto Averbuj
- Web page: https://patentgrep.com/patent/US10481202B2

## CPC

- G01R 31/31724: {Test controller, e.g. BIST state machine (for scan test G01R31/318555)}
- G01R 31/3183: Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R 31/3187: Built-in tests
- G01R 31/31921: {using compression techniques, e.g. patterns sequencer}
- G06F 11/2242: {in multi-processor systems, e.g. one processor becoming the primary tester (G06F11/2736 takes precedence)}
- G06F 11/27: Built-in tests
- G06F 11/36: Prevention of errors by analysis, debugging or testing of software
- G11C 29/10: Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
- G11C 29/36: Data generation devices, e.g. data inverters
- G01R 31/318547: {Data generators or compressors}
- G06F 9/4498: {Finite state machines}
- G11C 2029/3602: {Pattern generator}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A self-test controller includes a memory configured to store a test patterns, configuration registers, and a memory data component. The test patterns are encoded in the memory using various techniques in order to save storage space. By using the configuration parameters, the memory data component is configured to decode the test patterns and perform multiple built-in self-test on a multitude of test cores. The described techniques allow for built-in self-test to be performed dynamically while utilizing less space in the memory.

## Claims

### Claim 1

A self-test controller, comprising:
a memory configured to store a first test pattern that includes test subpatterns such that each of the test subpatterns includes test vectors and the test vectors in each of the test subpatterns correspond to a different test core of a plurality of test cores;
configuration registers configured to store configuration parameters that indicate a subset of the plurality of the test cores that are test enabled; and
a memory data component configured to upload the first test pattern and decode the test vectors in a subset of the test subpatterns that correspond to the subset of the plurality of the test cores that the configuration parameters indicate are test enabled.

### Claim 2 (depends on 1)

The self-test controller of claim 1, wherein the memory data component is configured to ignore the test vectors that are not in the subset of the test subpatterns corresponding to the subset of the plurality of the test cores that the configuration parameters indicate are test enabled.

### Claim 3 (depends on 1)

The self-test controller of claim 1, wherein the memory data component is configured to decode the test vectors in the subset of the test subpatterns to generate self-test test vectors.

### Claim 4 (depends on 1)

The self-test controller of claim 1, further comprising an interface operably associated with the plurality of the test cores, wherein the memory data component is configured to:
decode the test vectors in the subset of the test subpatterns so as to generate a self-test pattern that includes self-test subpatterns such that each of the self-test subpatterns includes self-test vectors corresponding to different ones of the subset of the plurality of the test cores that the configuration parameters indicate are test enabled; and
apply the self-test pattern to the subset of the plurality of the test cores through the interface such that the self-test subpatterns are implemented in parallel by the subset of the plurality of the test cores.

### Claim 5 (depends on 1)

The self-test controller of claim 1, wherein the memory is configured to store the test vectors of the test subpatterns such that each of the test vectors is encoded to include test data and a core identifier that identifies the corresponding test core of the plurality of test cores.

### Claim 6 (depends on 1)

The self-test controller of claim 1, wherein the memory is configured to store a second test pattern such that the first test pattern is a test subpattern included as a slice of the second test pattern.

### Claim 7 (depends on 1)

The self-test controller of claim 1 wherein the memory data component comprises a memory data finite state machine.

### Claim 8 (depends on 1)

The self-test controller of claim 1, wherein:
the memory is further configured to store a first encoded test vector that includes a first data field with first test data, a first repetition field with a first repetition value, and a first operational code that indicates that the first encoded test vector includes the first data field with the first test data and the first repetition field with the first repetition value; and
the memory data component is configured to:
upload the first encoded test vector from the memory;
read the first operational code;
extract the first test data from the first data field and the first repetition value from the first repetition field of the first encoded test vector in response to reading the first operational code; and
generate a first set of test vectors in response to extracting the first test data and the first repetition value, wherein each test vector in the first set of the test vectors includes test data that is a copy of the first test data and a number of the test vectors in the first set of the test vectors corresponds to the first repetition value.

### Claim 9 (depends on 1)

The self-test controller of claim 1, wherein:
the memory is further configured to store a first encoded test vector and a second encoded test vector wherein the first encoded test vector includes a first data field with first test data and a first operational code that indicates that the first encoded test vector includes the first data field and wherein the second encoded test vector includes a first repetition field with a first repetition value and a second operational code that indicates that the second encoded test vector includes the first repetition field; and
the memory data component is further configured to:
upload the first encoded test vector from the memory;
read the first operational code;
extract the first test data from the first data field of the first encoded test vector in response to reading the first operational code;
generate a first test vector in a first set of the test vectors in response to extracting the first test data;
upload the second encoded test vector from the memory;
read the second operational code;
extract the first repetition value from the first repetition field of the second encoded test vector in response to reading the second operational code; and
generate other test vectors in the first set of the test vectors in response to extracting the first repetition value, wherein each test vector in the first set of the test vectors includes test data that is a copy of the first test data and a number of the test vectors in the first set of the test vectors corresponds to the first repetition value.

### Claim 10

A method, comprising:
storing a first test pattern that includes test subpatterns in a memory such that each of the test subpatterns includes test vectors and the test vectors in each of the test subpatterns correspond to a different test core of a plurality of test cores;
storing configuration parameters that indicate a subset of the plurality of the test cores that are test enabled in configuration registers;
uploading the first test pattern from the memory with a memory data component; and
decoding the test vectors in a subset of the test subpatterns that correspond to the subset of the plurality of the test cores that the configuration parameters indicate are test enabled with the memory data component.

### Claim 11 (depends on 10)

The method of claim 10, further comprising ignoring the test vectors that are not in the subset of the test subpatterns corresponding to the subset of the plurality of the test cores that the configuration parameters indicate are test enabled.

### Claim 12 (depends on 10)

The method of claim 10, wherein the decoding the test vectors in the subset of the test subpatterns comprises generating self-test test vectors.

### Claim 13 (depends on 10)

The method of claim 10, wherein an interface is operably associated with the plurality of the test cores, wherein the decoding the test vectors in the subset of the test subpatterns comprises generating a self-test pattern that includes self-test subpatterns such that each of the self-test subpatterns includes self-test vectors corresponding to different one of the subset of the plurality of the test cores that the configuration parameters indicate are test enabled and wherein the method further comprises:
applying the self-test pattern to the subset of the plurality of the test cores through the interface such that the self-test subpatterns are implemented in parallel by the subset of the plurality of the test cores.

### Claim 14 (depends on 10)

The method of claim 10, wherein the memory is configured to store the test vectors of the test subpatterns such that each of the test vectors is encoded to include test data and a core identifier that identifies the corresponding test core of the plurality of test cores.

### Claim 15 (depends on 10)

The method of claim 10, wherein the memory is configured to store a second test pattern such that the first test pattern is a test subpattern included as a slice of the second test pattern.

### Claim 16 (depends on 10)

The method of claim 10 wherein the memory data component comprises a memory data finite state machine.

### Claim 17 (depends on 10)

The method of claim 10, further comprising:
storing a first encoded test vector in the memory, wherein the first encoded test vector includes a first data field with first test data, a first repetition field with a first repetition value, and a first operational code that indicates that the first encoded test vector includes the first data field with the first test data and the first repetition field with the first repetition value; and
uploading the first encoded test vector from the memory to the memory data component;
reading the first operational code;
extracting the first test data from the first data field and the first repetition value from the first repetition field of the first encoded test vector in response to reading the first operational code; and
generating a first set of test vectors in response to extracting the first test data and the first repetition value with the memory data component, wherein each test vector in the first set of the test vectors includes test data that is a copy of the first test data and a number of the test vectors in the first set of the test vectors corresponds to the first repetition value.

### Claim 18 (depends on 10)

The method of claim 10, further comprising:
storing a first encoded test vector and a second encoded test vector in the memory wherein the first encoded test vector includes a first data field with first test data and a first operational code that indicates that the first encoded test vector includes the first data field and wherein the second encoded test vector includes a first repetition field with a first repetition value and a second operational code that indicates that the second encoded test vector includes the first repetition field;
uploading the first encoded test vector from the memory to the memory data component;
reading the first operational code;
extracting the first test data from the first data field of the first encoded test vector in response to reading the first operational code;
generating a first test vector in a first set of the test vectors with the memory data component in response to extracting the first test data;
uploading the second encoded test vector from the memory to the memory data component;
reading the second operational code;
extracting the first repetition value from the first repetition field of the second encoded test vector in response to reading the second operational code; and
generating other test vectors in the first set of the test vectors with the memory data component in response to extracting the first repetition value, wherein each test vector in the first set of the test vectors includes test data that is a copy of the first test data and a number of the test vectors in the first set of the test vectors corresponds to the first repetition value.

### Claim 19

A non-transitory computer-readable medium (CRM) storing computer executable code, comprising code to:
store a first test pattern that includes test subpatterns in a memory such that each of the test subpatterns includes test vectors and the test vectors in each of the test subpatterns correspond to a different test core of a plurality of test cores;
store configuration parameters that indicate a subset of the plurality of the test cores that are test enabled in configuration registers;
upload the first test pattern from the memory with a memory data component; and
decode the test vectors in a subset of the test subpatterns that correspond to the subset of the plurality of the test cores that the configuration parameters indicate are test enabled with the memory data component.

### Claim 20 (depends on 19)

The CRM of claim 19, wherein the code is configured to ignore the test vectors that are not in the subset of the test subpatterns corresponding to the subset of the plurality of the test cores that the configuration parameters indicate are test enabled.

### Claim 21 (depends on 19)

The CRM of claim 19, wherein the code is configured to decode the test vectors in the subset of the test subpatterns by generating self-test test vectors.

### Claim 22 (depends on 19)

The CRM of claim 19, wherein an interface is operably associated with the plurality of the test cores and wherein the code is configured to decode the test vectors in the subset of the test subpatterns by generating a self-test pattern that includes self-test subpatterns such that each of the self-test subpatterns includes self-test vectors corresponding to different one of the subset of the plurality of the test cores that the configuration parameters indicate are test enabled and wherein the code is further configured to apply the self-test pattern to the subset of the plurality of the test cores through the interface such that the self-test subpatterns are implemented in parallel by the subset of the plurality of the test cores.

### Claim 23 (depends on 19)

The CRM of claim 19, wherein the memory is configured to store the test vectors of the test subpatterns such that each of the test vectors is encoded to include test data and a core identifier that identifies the corresponding test core of the plurality of test cores.

### Claim 24 (depends on 19)

The CRM of claim 19, wherein the memory is configured to store a second test pattern such that the first test pattern is a test subpattern included as a slice of the second test pattern.

### Claim 25 (depends on 19)

The CRM of claim 19, wherein the memory data component comprises a memory data finite state machine.

### Claim 26 (depends on 19)

The CRM of claim 19, wherein the code is further configured to:
store a first encoded test vector in the memory, wherein the first encoded test vector includes a first data field with first test data, a first repetition field with a first repetition value, and a first operational code that indicates that the first encoded test vector includes the first data field with the first test data and the first repetition field with the first repetition value; and
upload the first encoded test vector from the memory to the memory data component;
read the first operational code;
extract the first test data from the first data field and the first repetition value from the first repetition field of the first encoded test vector in response to reading the first operational code; and
generate a first set of test vectors in response to extracting the first test data and the first repetition value with the memory data component, wherein each test vector in the first set of the test vectors includes test data that is a copy of the first test data and a number of the test vectors in the first set of the test vectors corresponds to the first repetition value.

### Claim 27 (depends on 19)

The CRM of claim 19, wherein the code is further configured to:
store a first encoded test vector and a second encoded test vector in the memory wherein the first encoded test vector includes a first data field with first test data and a first operational code that indicates that the first encoded test vector includes the first data field and wherein the second encoded test vector includes a first repetition field with a first repetition value and a second operational code that indicates that the second encoded test vector includes the first repetition field;
upload the first encoded test vector from the memory to the memory data component;
read the first operational code;
extract the first test data from the first data field of the first encoded test vector in response to reading the first operational code;
generate a first test vector in a first set of the test vectors with the memory data component in response to extracting the first test data;
upload the second encoded test vector from the memory to the memory data component;
read the second operational code;
extract the first repetition value from the first repetition field of the second encoded test vector in response to reading the second operational code; and
generate other test vectors in the first set of the test vectors with the memory data component in response to extracting the first repetition value, wherein each test vector in the first set of the test vectors includes test data that is a copy of the first test data and a number of the test vectors in the first set of the test vectors corresponds to the first repetition value.