# US 10,479,075 B2 · Print head substrate and method of manufacturing the same, and semiconductor substrate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,479,075 B2 - Document ID: US10479075B2 - Status: Granted - Kind: B2 - Application number: 15/953,553 - Filed: 2018-04-16 - Published: 2018-11-15 - Granted: 2019-11-19 - Earliest claimed: 2017-05-09 - Assignees: Canon Kabushiki Kaisha - Applicants: Canon Kabushiki Kaisha - Inventors: Ryo Kasai; Masataka Sakurai; Koichi Ishida - Web page: https://patentgrep.com/patent/US10479075B2 ## CPC - B41J 2/14072: {Electrical connections, e.g. details on electrodes, connecting the chip to the outside...} - B41J 2/155: for line printing - B41J 2/1601: {Production of bubble jet print heads (B41J2/1606, B41J2/162 take precedence)} - B41J 2/1635: {dividing the wafer into individual chips} - B41J 2/2103: {Features not dealing with the colouring process per se, e.g. construction of printers or heads, driving circuit adaptations} - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - H10W 20/484: {Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes} - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - B41J 2202/13: Heads having an integrated circuit - B41J 2202/18: Electrical connection established using vias - B41J 2202/20: Modules - H10W 46/503: {Located in scribe lines} - B41J: TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A print head substrate includes: a substrate surface including a plurality of printing elements and a plurality of pads disposed along a first side and electrically connected to the printing elements, the substrate surface having an acute angle portion formed by the first side and a second side; and a test element group (TEG) area including a TEG not electrically connected to the printing elements, at least a part of the TEG area being located between the second side and a pad closest to a vertex of the acute angle portion among the pads. ## Claims ### Claim 1 A print head substrate comprising: a substrate surface including a plurality of printing elements and a plurality of pads disposed along a first side and electrically connected to the printing elements, the substrate surface having an acute angle portion formed by the first side and a second side; and a test element group (TEG) area including a TEG not electrically connected to the printing elements, at least a part of the TEG area being located between the second side and a pad closest to a vertex of the acute angle portion among the pads. ### Claim 2 (depends on 1) The print head substrate according to claim 1, wherein the TEG area does not overlap with an area in which the printing elements are disposed. ### Claim 3 (depends on 1) The print head substrate according to claim 1, wherein the substrate surface has a plurality of the acute angle portions, and the TEG area is disposed at a position corresponding to at least one of vertexes of the acute angle portions. ### Claim 4 (depends on 1) The print head substrate according to claim 1, wherein a shape of the substrate surface is a parallelogram. ### Claim 5 (depends on 1) The print head substrate according to claim 1, wherein a shape of the substrate is a trapezoid. ### Claim 6 (depends on 1) The print head substrate according to claim 1, wherein the TEG includes at least one of a transistor, wiring, a resistance element, a printing element, and a plug, and the TEG and a second pad connected to the TEG are disposed in the TEG area. ### Claim 7 (depends on 1) The print head substrate according to claim 1, wherein the TEG is used for process monitoring of managing a wafer manufacturing process. ### Claim 8 (depends on 1) The print head substrate according to claim 1, wherein the TEG is used for obtaining a device characteristic of the printing elements. ### Claim 9 (depends on 1) The print head substrate according to claim 1, wherein at least two of the printing elements are connected in common to a wiring trace extended from the pads. ### Claim 10 (depends on 9) The print head substrate according to claim 9, wherein the wiring trace does not overlap with the TEG area. ### Claim 11 (depends on 9) The print head substrate according to claim 9, wherein an area including the pads, the wiring trace, and the printing elements is separated from the TEG area by a moisture-resistant ring. ### Claim 12 (depends on 11) The print head substrate according to claim 11, wherein the moisture-resistant ring surrounds an area including the pads, the wiring trace, and the printing elements, and the TEG area is disposed outside the moisture-resistant ring. ### Claim 13 (depends on 11) The print head substrate according to claim 11, wherein the print head substrate includes a second moisture-resistant ring surrounding the TEG area. ### Claim 14 (depends on 1) The print head substrate according to claim 1, wherein the substrate surface has an obtuse angle portion formed by the first side and a third side opposed to the second side, and a distance between the second side and a pad closest to the vertex of the acute angle portion among the pads is larger than a distance between the third side and a pad closest to a vertex of the obtuse angle portion among the pads. ### Claim 15 A method of manufacturing a print head substrate, the print head substrate including: a substrate surface including a plurality of printing elements and a plurality of pads disposed along a first side and electrically connected to the printing elements, the substrate surface having an acute angle portion formed by the first side and a second side; and a test element group (TEG) area including a TEG not electrically connected to the printing elements, at least a part of the TEG area being located between the second side and a pad closest to a vertex of the acute angle portion among the pads, the method comprising: forming a pattern of an affected layer inside a wafer substrate; and cutting out the print head substrate having the acute angle portion by cleaving the wafer substrate along the formed pattern. ### Claim 16 A semiconductor substrate comprising: a substrate surface including a plurality of elements and a plurality of pads disposed along a first side and electrically connected to the elements, the substrate surface having an acute angle portion formed by the first side and a second side; and a test element group (TEG) area including a TEG not electrically connected to the elements, at least a part of the TEG area being located between the second side and a pad closest to a vertex of the acute angle portion among the pads. ### Claim 17 (depends on 16) The semiconductor substrate according to claim 16, wherein the TEG area does not overlap with an area in which the elements are disposed. ### Claim 18 (depends on 16) The semiconductor substrate according to claim 16, wherein a shape of the substrate surface is a parallelogram. ### Claim 19 (depends on 16) The semiconductor substrate according to claim 16, wherein at least two of the elements are connected in common to a wiring trace extended from the pads. ### Claim 20 (depends on 19) The semiconductor substrate according to claim 19, wherein the wiring trace does not overlap with the TEG area.