Apparatuses, systems, and methods for performing hardware acceleration via dual-compact-form-factor expansion cards

A system comprising:

• a central processing unit;
• at least one memory device;
• at least one expansion socket;
• and
• at least one expansion card that comprises:
• a printed circuit board;
• at least one hardware accelerator, disposed on the printed circuit board, that:
• comprises application-specific hardware circuitry designed to perform a computing task;
• and
• offloads at least a portion of the computing task from the central processing unit by executing, via the application-specific hardware circuitry, the portion of the computing task;
• and
• an edge connector, disposed on a connecting edge of the printed circuit board, that is dimensioned to be inserted into the expansion socket, wherein the edge connector:
• couples the hardware accelerator to the central processing unit via a computing bus connected to the expansion socket when the expansion card is inserted into the expansion socket;
• and
• comprises a primary pinout, disposed within a primary portion of the edge connector, and a secondary pinout, disposed within a secondary portion of the edge connector, wherein:
• each of the primary pinout and the secondary pinout conform to a compact pinout specification included in a compact expansion card specification;
• and
• the compact pinout specification is more compact than a pinout specification defined for the computing bus.

A method comprising:

• disposing at least one hardware accelerator on a printed circuit board, wherein the hardware accelerator:
• comprises application-specific hardware circuitry designed to perform a computing task;
• and
• offloads at least a portion of the computing task from a central processing unit of a computing device by executing, via the application-specific hardware circuitry, the portion of the computing task;
• forming, on a connecting edge of the printed circuit board, an edge connector that is dimensioned to be inserted into an expansion socket of the computing device and that couples the hardware accelerator to the central processing unit via a computing bus connected to the expansion socket when inserted into the expansion socket by forming:
• a primary pinout within a primary portion of the edge connector;
• and
• a secondary pinout within a secondary portion of the edge connector;
• wherein:
• each of the primary pinout and the secondary pinout conform to a compact pinout specification included in a compact expansion card specification;
• and
• the compact pinout specification is more compact than a pinout specification defined for the computing bus.