US 10,477,626 B2 · Hard switching disable for switching power device

Abstract

A controller for driving a power switch incorporates a hard turn-on disable circuit to prevent the power switch from turning on when the power switch is sustaining a high voltage value. The hard turn-on disable circuit includes a hard turn-on detection circuit and a protection logic circuit. The hard turn-on disable circuit is configured to block or to pass the system input signal to the normal gate drive circuit of the power switch depending on the detection indicator signal. In particular, the protection logic circuit blocks the system input signal VIN in response to a high voltage detection so that the power switch ignores the system input signal VIN, which may be erroneous, and the power switch is prevented from undesirable hard switching.

Claims15

Dependent claims

A controller circuit for generating a gate drive signal on an output node for driving a gate terminal of a power switch where the gate terminal controls the current flow between first and second power terminals of the power switch, the controller circuit comprising:

a first gate drive circuit configured to receive an input control signal and to generate a first output signal as the gate drive signal to drive the gate terminal of the power switch to turn on and off the power switch responsive to the input control signal, the first output signal having a first gate voltage value to drive the gate terminal of the power switch to turn on the power switch;
and
a hard turn-on disable circuit configured to generate the input control signal in response to a system input signal and a first voltage indicative of a voltage across the first and second power terminals of the power switch, the system input signal determining an on-period and off-period of the power switch, the hard turn-on disable circuit generating a high voltage indicator signal, the high voltage indicator signal being asserted in response to the first voltage exceeding a first threshold level and being deasserted otherwise,
wherein while the power switch is in an off state in response to the system input signal and in response to the high voltage indicator signal being asserted, the hard turn-on disable circuit generates the input control signal having a first logical state to block the system input signal from being provided to the first gate drive circuit, and in response to the high voltage indicator signal being deasserted, the hard turn-on disable circuit generates the input control signal mirroring the system input signal to drive the first gate drive circuit.

1 more element

A method of generating a gate drive signal for driving a gate terminal of a power switch where the gate terminal controls the current flow between first and second power terminals of the power switch, the method comprising:

monitoring a feedback voltage indicative of a voltage across the first and second power terminals of the power switch;
providing a high voltage indicator signal;
determining the feedback voltage exceeding a first threshold level during the off-period of the power switch;
in response to the determining the feedback voltage exceeding the first threshold level, asserting the high voltage indicator signal;
determining the feedback voltage being below the first threshold level during the off-period of the power switch;
in response to the determining the feedback voltage being below the first threshold level, deasserting the high voltage indicator signal;
in response to the high voltage indicator signal being deasserted during the off-period of the power switch, providing a system input signal to drive the power switch to turn on and off, the system input signal determining an on-period and off-period of the power switch;
and
in response to the high voltage indicator signal being asserted during the off-period of the power switch, blocking the system input signal from the power switch, the power switch being turned off regardless of the states of the system input signal.

6 more elements

a first gate drive circuit configured to receive an input control signal and to generate a first output signal as the gate drive signal to drive the gate terminal of the power switch to turn on and off the power switch responsive to the input control signal, the first output signal having a first gate voltage value to drive the gate terminal of the power switch to turn on the power switch;
a first protection circuit configured to generate the input control signal in response to a system input signal and a feedback voltage indicative of a voltage across the first and second power terminals of the power switch, the system input signal determining an on-period and off-period of the power switch, while the power switch is in an off state in response to the system input signal and in response to the feedback voltage exceeding a first threshold level, the first protection circuit being configured to generate the input control signal to block the system input signal from being provided to the first gate drive circuit;
and
a second protection circuit configured to receive the feedback voltage and to generate a fault detection indicator signal, the protection circuit asserting the fault detection indicator signal in response to the feedback voltage exceeding a second threshold level, the second threshold level being higher than the first threshold level, the second protection circuit being configured to generate a second output signal as the gate drive signal to turn on the power switch at a second gate voltage value for a predetermined time duration in response to the fault detection indicator signal being asserted while the power switch is in an off state in response to the system input signal.

1 more element

Dependencies are inferred from the claim text.

Hard switching disable for switching power device

Life of this patent

Hard switching disable for switching power device

Life of this patent

Abstract

Claims15