Dual eclipse circuit for reduced image sensor shading

In an imaging array having a plurality of pixel sensor cells arranged in a plurality of rows and columns, pixel data being read out on column lines of the array, two column line anti-eclipse voltage clamp circuits for column lines in the array comprising:

• a first anti-eclipse voltage clamp circuit coupled to the top of each of the columns of pixels, which forms a row at a top of the array;
• a second anti-eclipse voltage clamp circuit coupled to the bottom of each of the column of pixels, which forms a row at a bottom of the array;
• wherein the employment of the two anti-eclipse voltage clamp circuits reduces a settling time of the anti-eclipse clamp voltage which reduces a top to bottom or vertical shading of an image captured and read out from the imaging array;
• and
• wherein each anti-eclipse voltage clamp circuit comprises three MOS transistors coupled between a power supply and the column line comprising:
• a diode-connected transistor with its gate and drain connected to the power supply;
• and
• a variable clamp voltage level setting transistor with its drain connected to the source of the diode-connected transistor;
• and
• a clamp enable transistor with its drain connected to the source of the clamp voltage level setting transistor and it source connected to the column line.