Equalizer circuit, receiver circuit, and integrated circuit device

An equalizer circuit comprising:

• a first adder circuit configured to add an input signal and including an addition terminal and a subtraction terminal;
• a comparator circuit configured to compare an output signal of the first adder circuit;
• a latch circuit configured to latch data output from the comparator circuit;
• a digital/analog converter circuit configured to output a third signal corresponding to an absolute value of an equalizing coefficient;
• and
• a switch circuit configured to switch a connection between an output terminal of the digital/analog converter circuit, and a set of the addition terminal and the subtraction terminal, based on the data latched in the latch circuit and sign information of the equalizing coefficient.

An equalizer circuit comprising:

• a first adder circuit configured to add an input signal and including an addition terminal and a subtraction terminal;
• a comparator circuit configured to compare an output signal of the first adder circuit;
• a latch circuit configured to latch a first value based on data output from the comparator circuit;
• a digital/analog converter circuit configured to output a fourth signal corresponding to an absolute value of an equalizing coefficient;
• and
• a switch circuit configured to switch a connection between an output terminal of the digital/analog converter circuit, and a set of the addition terminal and the subtraction terminal, wherein
• the first value is a value obtained by multiplying the data output from the comparator circuit and sign information of the equalizing coefficient.