Hybrid half/quarter-rate DFE
AssigneeSamsung Display Co., Ltd.
InventorsAnup P. Jose, Amir Amirkhany, Mohammad Hekmat
Life of this patent
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Abstract
A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.
Claims20
A two-stage decision feedback equalizer for receiving serial data, at an analog input, at a first data rate,
- the two-stage decision feedback equalizer comprising:
- a first stage, comprising a half-rate predictive decision feedback equalizer having:
- an analog input connected to the analog input of the two-stage decision feedback equalizer,
- a first digital output, and
- a second digital output;
- and
- a second stage, comprising:
- a first flip flop having a data input connected to the first digital output,
- a second flip flop having a data input connected to the first digital output,
- a third flip flop having a data input connected to the second digital output, and
- a fourth flip flop having a data input connected to the second digital output,
- the first stage being in a first clock domain configured to operate with a first clock at a frequency equal to one half of the first data rate, and
- the second stage being in a second clock domain configured to operate with a second clock at a frequency equal to one quarter of the first data rate.
A two-stage decision feedback equalizer for receiving serial data, at an analog input, at a first data rate,
- the two-stage decision feedback equalizer comprising:
- a first stage, connected to the analog input, the first stage comprising a half-rate predictive decision feedback equalizer comprising current mode logic circuits;
- and
- a second stage, connected to the first stage, the second stage comprising complementary metal oxide semiconductor circuits,
- the first stage being in a first clock domain configured to operate with a first clock at a frequency equal to one half of the first data rate, and
- the second stage being in a second clock domain configured to operate with a second clock at a frequency equal to one quarter of the first data rate.
A display, comprising:
- a timing controller having a serial data output;
- and
- a driver integrated circuit having an analog input for receiving serial data, at a first data rate,
- the driver integrated circuit comprising a two-stage decision feedback equalizer for receiving the serial data, the two-stage decision feedback equalizer having an analog input connected to the analog input of the driver integrated circuit,
- the two-stage decision feedback equalizer comprising:
- a first stage, connected to the analog input, the first stage comprising a half-rate predictive decision feedback equalizer comprising of current mode logic circuits;
- and
- a second stage, connected to the first stage, the second stage comprising complementary metal oxide semiconductor circuits,
- the first stage being in a first clock domain configured to operate with a first clock at a frequency equal to one half of the first data rate, and
- the second stage being in a second clock domain configured to operate with a second clock at a frequency equal to one quarter of the first data rate.
Dependencies are inferred from the claim text.