Equalizer circuit and control method of equalizer circuit
AssigneeToshiba Memory Corporation
InventorNaoki Kitazawa
Life of this patent
Estimating the term…
Abstract
According to one embodiment, an equalizer circuit includes a nonlinear equalizer including: a determination circuit configured to generate a second signal indicating a digital value of a first signal, based on a first clock signal; a clock generation circuit configured to generate a second clock signal having a time constant of a falling edge larger than a time constant of a rising edge, based on the first clock signal; and a feedback circuit configured to generate a third signal by feeding back the second signal to the first signal, based on the second clock signal.
Claims19
An equalizer circuit comprising a nonlinear equalizer, the nonlinear equalizer including:
- a determination circuit configured to generate a second signal indicating a digital value of a first signal, based on a first clock signal;
- a clock generation circuit configured to generate a second clock signal having a time constant of a falling edge larger than a time constant of a rising edge, based on the first clock signal;
- and
- a feedback circuit configured to generate a third signal by feeding back the second signal to the first signal, based on the second clock signal.
A control method for an equalizer circuit, comprising:
- generating a second signal indicating a digital value of a first signal, based on a first clock signal;
- generating a second clock signal having a time constant of a falling edge larger than a time constant of a rising edge, based on the first clock signal;
- and
- generating a third signal by feeding back the second signal to the first signal, based on the second clock signal.
Dependencies are inferred from the claim text.