SPDIF clock and data recovery with sample rate converter

An audio output signal transmitting system, comprising:

• a sample counter configured to be incremented by each sample of an input data stream received from a sample receiver responsive to a determination that the sample receiver has received at least one sample of the input data stream and the sample counter being further configured to be decremented by a toothless clock signal at a selected frequency that is not less than an expected frequency of the input data stream responsive to a determination that the sample receiver has not received at least one sample of the input data stream;
• a sample rate converter configured to accumulate samples from the sample receiver at a rate of the toothless clock signal;
• an AND gate configured to pass the toothless clock signal to the sample rate converter to interpolate samples received from the sample receiver to generate a Pulse Code Modulated output data stream having the selected frequency responsive to a determination that an output of the sample counter is greater than zero;
• a Universal Serial Bus sample receiver configured to send samples to the sample rate converter at the rate of the toothless clock signal;
• and
• a Universal Serial Bus-type transceiver configured to send Universal Serial Bus-type data to the Universal Serial Bus sample receiver.

A system for processing audio data, comprising:

• a sample receiver configured to receive at least one sample of an input data stream;
• a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received the at least one sample of the input data stream;
• a sample rate converter configured to accumulate samples from the sample receiver at a rate of a toothless clock signal;
• an AND gate configured to pass the toothless clock signal to the sample rate converter to interpolate samples received from the sample receiver to generate Pulse Code Modulated output data stream having a selected frequency that is not less than an expected frequency of the input data stream responsive to a determination that the output of the sample counter is greater than zero;
• and
• a sample output buffer configured to receive the output data stream at a frequency provided by a reference clock signal.