Method and system for implementing high speed source synchronous clock alignment
AssigneeCadence Design Systems, Inc.
InventorsSathish Kumar Ganesan, Fred Staples Stivers
Life of this patent
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Abstract
Disclosed is an improved approach to implement clock alignments between a test subject and its corresponding controller device. Phase locking is performed for the clocks between the test subject and controller device via a training sequence to obtain the appropriate alignment(s). Alignment logic is included on both the testchip and the controller device to implement alignment.
Claims19
A system for implementing high speed source synchronous clock alignment, comprising:
- a controller device, comprising:
- a first transmit (Tx) PRBS (pseudo-random binary sequence) generator that generates Tx PRBS data using a first Tx polynomial;
- a Tx phase shift controller coupled to a Tx Clock MMCM (Multi-Mode Clock Manager) that provides a Tx MMCM output clock to the first Tx PRBS generator;
- a receive (Rx) phase shift controller coupled to a Rx Clock MMCM (Multi-Mode Clock Manager) that provides a Rx MMCM output clock to a first Rx PRBS checker;
- the first Rx PRBS checker receiving Rx PRBS data;
- a test subject, comprising:
- a second Rx PRBS checker that receives the Tx PRBS data generated at the controller device;
- a second Tx PRBS generator that generates the Rx PRBS data using a second Tx polynomial received at the first Rx PRBS checker at the controller device, the first Tx polynomial being different from the second Tx polynomial;
- and
- a test structure register that holds status information corresponding to lock status of the Tx PRBS data and the Rx PRBS data.
A system for implementing high speed source synchronous clock alignment, comprising:
- a controller device, comprising:
- a transmit (Tx) PRBS (pseudo-random binary sequence) generator to generate Tx PRBS data;
- a receive (Rx) PRBS checker receiving Rx PRBS data;
- a Tx/Rx phase shift controller coupled to both a Tx Clock MMCM (Multi-Mode Clock Manager) and a Rx Clock MMCM;
- the Tx Clock MMCM providing a Tx MMCM clock to the Tx PRBS generator;
- the Rx Clock MMCM providing a Rx MMCM clock to the Rx PRBS checker;
- the Tx/Rx phase shift controller phase shifting the Tx MMCM clock and the Rx MMCM clock;
- and
- a test subject, comprising:
- a FIFO device that stores the Tx PRBS data from the controller device and which retransmits the Tx PRBS data as the Rx PRBS data from the test subject to the controller device, wherein the Tx PRBS data is captured using a first clock, the Rx PRBS data is transmitted using a second clock, and the first clock is different from the second clock.
A method for implementing source synchronous clock alignment, comprising:
- (a) generating, at a controller device, first transmit (Tx) PRBS (pseudo-random binary sequence) data using a first Tx polynomial;
- (b) transmitting the first Tx PRBS data between the controller device to a test subject;
- (c) checking the first Tx PRBS data for lock status using a given clock offset;
- (d) iteratively performing (a) through (c) until a first lock has been achieved;
- (e) generating, at the test subject, second Tx PRBS data for transmission using a second Tx polynomial;
- (f) transmitting the second Tx PRBS data between the test subject and the controller device;
- (g) checking the second Tx PRBS data for lock status using a given clock offset;
- and
- (h) iteratively performing (e) through (g) until a second lock has been achieved.
Dependencies are inferred from the claim text.