Device and method for supporting clock transfer of multiple clock domains
AssigneeHuawei Technologies Co., Ltd.
InventorJinhui Wang
Life of this patent
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Abstract
A device and a method for supporting clock transfer of multiple clock domains, where the device includes N phase frequency detectors, N filters, N clock reconstructors, and N clock domain interfaces, where N is an integer greater than or equal to two, the N clock domain interfaces are in a one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors, the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different. The foregoing device flexibly adapt to multiple different clock domains, implement that a single device simultaneously supports clock transfer of multiple clock domains, and flexibly satisfy user demands without adding or replacing devices.
Claims20
A method implemented by a device, comprising:
- receiving N clock signals, wherein at least two clock signals of the N clock signals are different, and wherein the N is an integer greater than or equal to two;
- determining N pieces of phase difference information between the N clock signals and a common reference clock respectively;
- acquiring N pieces of frequency difference information based on the N pieces of phase difference information respectively;
- reconstructing N network timing clocks in the device based on the common reference clock signal and the N pieces of frequency difference information;
- and
- sending the N network timing clocks to N clock domain interfaces respectively, wherein the N network timing clocks are in a one-to-one correspondence with the N clock domain interfaces.
A non-transitory computer readable medium storing a program causing a computer to execute a process comprising:
- receiving N clock signals, wherein at least two clock signals of the N clock signals are different, and wherein the N is an integer greater than or equal to two;
- determining N pieces of phase difference information between the N clock signals and a common reference clock respectively;
- acquiring N pieces of frequency difference information based on the N pieces of phase difference information respectively;
- reconstructing N network timing clocks in the device based on the common reference clock signal and the N pieces of frequency difference information;
- and
- sending the N network timing clocks to N clock domain interfaces respectively, wherein the N network timing clocks are in a one-to-one correspondence with the N clock domain interfaces.
A device, comprising:
- N phase frequency detectors configured to:
- receive N clock signals, wherein at least two clock signals of the N clock signals are different, wherein the N is an integer greater than or equal to two;
- and
- determine N pieces of phase difference information between the N clock signals and a common reference clock respectively;
- N filters configured to acquire N pieces of frequency difference information based on the N pieces of phase difference information respectively;
- and
- N clock reconstructors configured to:
- reconstruct N network timing clocks in the device based on the common reference clock signal and the N pieces of frequency difference information;
- and
- send the N network timing clocks to N clock domain interfaces respectively, wherein the N network timing clocks are in a one-to-one correspondence with the N clock domain interfaces.
Dependencies are inferred from the claim text.