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US 10,476,580 B2Granted
High speed phase shift keying modulator
AssigneeGenohco Inc.
InventorsTae Sam Yoo, Ho Jik Lee
Life of this patent
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Abstract
Provided is a high speed phase shift keying modulator. The high speed phase shift keying modulator has variable pipeline buffers formed at an input side and an output side of a bandlimiting filter and a compensation filter to ensure timing margins of the bandlimiting filter and the compensation filter, so that a ultra-high speed phase shift keying modulator is provided.
Claims2
A high speed phase shift keying modulator, comprising:
- a mapper configured to map a signal to modulating symbols representing a position according to an amplitude and a phase constellation;
- a first pipeline buffer having an in-phase component of an output of the mapper as an input;
- a second pipeline buffer having a quadrature phase component of the output of the mapper as an input;
- a first square root raised cosine (SRRC) filter having an output signal of the first pipeline buffer as an input;
- a second SRRC filter having an output signal of the second pipeline buffer as an input;
- a third pipeline buffer having an output signal of the first SRRC filter as an input;
- a fourth pipeline buffer having an output signal of the second SRRC filter as an input;
- a first compensation filter having an output signal of the third pipeline buffer as an input, and configured to compensate for signal distortion;
- a second compensation filter having an output signal of the fourth pipeline buffer as an input, and configured to compensate for signal distortion;
- a first digital-analog converter (DAC) having an output signal of the first compensation filter as an input;
- and
- a second DAC having an output signal of the second compensation filter as an input,
- wherein each of the first SRRC filter and the second SRRC filter includes
- an odd number portion finite impulse response filter configured to process an odd number component of an input signal,
- an even number portion finite impulse response filter configured to process an even number component of the input signal, and
- a summator configured to summate outputs of the odd number portion finite impulse response filter and the even number portion finite impulse response filter, and to output a result of the summation,
- wherein the high speed phase shift keying modulator is implemented using a field programmable gate array (FPGA), and
- wherein the first to fourth pipeline buffers have a pipeline state value which is determined with reference to a slack value of a slack report generated after automatic placement and routing (P&R).
15 more elements
Dependencies are inferred from the claim text.