Continuous time linear capacitive digital step attenuator

A digital step attenuator (DSA), comprising:

• a first input terminal configured to receive an input signal;
• a termination resistor bank coupled to the first input terminal and comprising:
• a series resistor coupled to the first input terminal,
• a set of one or more termination resistors coupled to the series resistor, and
• a set of termination switches coupled between the set of one or more termination resistors and a first fixed voltage terminal, each termination switch coupled between a termination resistor and the first fixed voltage terminal;
• a series capacitor bank coupled to the first input terminal and a first output terminal;
• and
• a shunt capacitor bank coupled to the first output terminal,
• wherein the first output terminal is configured to provide an attenuated signal.

A computing device comprising:

• a processing unit;
• a memory module coupled to the processing unit
• an RF receiver coupled to the processing unit and the memory module, the RF receiver further comprising:
• an input driver configured to receive a coarse signal, and configured to generate an input signal;
• a digital step attenuator (DSA) coupled to the input driver, configured to receive the input signal, and configured to generate an attenuated signal, wherein the DSA comprises:
• a termination resistor bank coupled to the input driver,
• a series capacitor bank coupled to the input driver and a buffer, and
• a shunt capacitor bank coupled to the buffer;
• the buffer coupled to the DSA, configured to receive the attenuated signal, and configured to output the attenuated signal;
• and
• an analog to digital converter (ADC) coupled to the buffer, configured to receive the attenuated signal from the buffer, and configured to generate an output signal.