Error detection code generation circuits of semiconductor devices, memory controllers including the same and semiconductor memory devices including the same

A memory controller, comprising:

• an error detection code generation circuit configured to generate first error detection code bits based on a plurality of first unit data and first data bus inversion (DBI) bits, wherein each of the first DBI bits indicates whether a corresponding bit of the first unit data is inverted, to generate second error detection code bits based on a plurality second unit data and second DBI bits, wherein each of the second DBI bits indicates whether a corresponding bit of the second unit data is inverted, to select one of a most significant bit of the second error detection code bits and an inverted version of the most significant bit of the second error detection code bits in response to a mode signal, to output the selected error detection code bit and to generate final error detection code bits by merging the first error detection code bits, the second error detection code bits and the selected error detection code bit, wherein the mode signal indicates a code rate mode and the first unit data and the second unit data are included in a main data;
• and
• an error detector configured to detect errors of the main data which is to be transmitted to a semiconductor memory device, based on return final error detection code bits and the final error detection code bits, wherein the semiconductor memory device is configured to receive the main data, the first DBI bits and the second DBI bits to generate the return final error detection code bits,
• wherein the error detection code generation circuit is configured to generate the first error detection code bits and the second error detection code bits by using a same generation matrix.

An error detection code generation circuit for a semiconductor memory device, the error detection code generation circuit comprising:

• a first cyclic redundancy check (CRC) engine configured to receive first unit data and to generate first error detection code bits based on the first unit data;
• a second CRC engine configured to receive second unit data and to generate second error detection code bits based on the second unit data;
• a multiplexer configured to select one of a most significant bit of the second error detection code bits and an inverted version of the most significant bit of the second error detection code bits in response to a mode signal;
• and
• an XOR circuit configured to receive the first error detection code bits and the second error detection code bits, and to merge the first error detection code bits, the second error detection code bits and the selected one of the second error detection code bits into final error detection code bits by performing an exclusive OR function,
• wherein the first error detection code bits and the second error detection code bits are output in a full rate mode in response to a first level of the mode signal and the final detection code bits are output in a half rate mode in response to a second level of the mode signal.