Low latency bit-reversed polar codes

A method of wireless communication of a receiver device, comprising:

• receiving a signal from a transmitter device, the signal including at least in part m consecutive elements, wherein m=2k and k is a positive integer representing a number of information bits;
• determining indices associated with each of the m consecutive elements, each of the m consecutive elements associated with a different index;
• bit reversing a binary sequence associated with each of the m consecutive elements, each of the m consecutive elements include a different binary sequence;
• determining, after bit reversing, a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m consecutive elements;
• and
• writing each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices, the different memory bank for each of the m consecutive elements being selected based on a most significant log 2(m) bits associated with each of the m consecutive elements after the bit-reversed order of the indices is determined.

An apparatus for wireless communication of a transmitter device, comprising:

• means for determining indices associated with m consecutive elements, wherein m=2k and k is a positive integer representing a number of information bits, and wherein each of the m consecutive elements are associated with a different index;
• means for bit reversing a binary sequence associated with each of the m consecutive elements, each of the m consecutive elements including a different binary sequence;
• means for determining, after bit reversing, a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m consecutive elements;
• means for writing each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices, the different memory bank for each of the m consecutive elements being selected based on a most significant log 2(m) bits associated with each of the m consecutive elements after the bit-reversed order of the indices is determined;
• and
• means for transmitting a signal that includes at least the m consecutive elements to a receiver device.

An apparatus for wireless communication of a transmitter device, comprising:

• at least one memory bank;
• at least one processor coupled the at least one memory bank and configured to:
• determine indices associated with m consecutive elements, wherein m=2k and k is a positive integer representing a number of information bits, and wherein each of the m consecutive elements are associated with a different index;
• bit reverse a binary sequence associated with each of the m consecutive elements, each of the m consecutive elements including a different binary sequence;
• determine, after bit reversing, a bit-reversed order of the indices based at least in part on the bit-reversed binary sequence associated with each of the m consecutive elements;
• write each of the m consecutive elements to a different memory bank in parallel based at least in part on the bit-reversed order of the indices, the different memory bank for each of the m consecutive elements being selected based on a most significant log 2(m) bits associated with each of the m consecutive elements after the bit-reversed order of the indices is determined;
• and
• transmit a signal that includes at least the m consecutive elements to a receiver device.