SAR ADC with high linearity
AssigneesNCKU Research and Development Foundation, Himax Technologies Limited
InventorsSoon-Jyh Chang, Li-Jen Chang
Life of this patent
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Abstract
A successive approximation register (SAR) analog-to-digital converter (ADC) with high linearity for generating an n-bit converted output includes a first capacitor digital-to-analog (DAC) and a second capacitor DAC. One of the first capacitor DAC and the second capacitor DAC that has greater output signal is defined as a higher-voltage capacitor DAC, and the other as an un-switching capacitor DAC. In an m-th conversion phase, an (m−1)-th capacitor of the un-switching capacitor DAC is switched according to a comparison between output signals of the higher-voltage capacitor DAC and the un-switching capacitor DAC.
Claims20
A successive approximation register (SAR) analog-to-digital converter (ADC) with high linearity for generating an n-bit converted output, comprising:
- a first capacitor digital-to-analog (DAC);
- and
- a second capacitor DAC;
- wherein in sampling phase, switching all capacitors of the first capacitor DAC and the second capacitor DAC to a common voltage;
- in a first conversion phase, determining a first most-significant-bit (MSB) of the converted output according to a comparison between output signals of the first capacitor DAC and the second capacitor DAC;
- defining one of the first capacitor DAC and the second capacitor DAC that has greater output signal as a higher-voltage capacitor DAC, and the other of the first capacitor DAC and the second capacitor DAC as an un-switching capacitor DAC;
- switching all capacitors of the higher-voltage capacitor DAC to ground, the common voltage being greater than the ground but less than a power supply;
- in an m-th conversion phase (1<m<n), determining an m-th MSB of the converted output according to a comparison between output signals of the first capacitor DAC and the second capacitor DAC;
- switching an (m−1)-th capacitor of the un-switching capacitor DAC according to a comparison between output signals of the higher-voltage capacitor DAC and the un-switching capacitor DAC;
- and
- in an n-th conversion phase, determining a least significant bit (LSB) of the converted output according to a comparison between output signals of the first capacitor DAC and the second capacitor DAC.
A successive approximation register (SAR) analog-to-digital converter (ADC) with high linearity for generating an n-bit converted output, comprising:
- a first capacitor digital-to-analog (DAC);
- and
- a second capacitor DAC;
- wherein in sampling phase, switching all capacitors of the first capacitor DAC and the second capacitor DAC to a common voltage;
- in a first conversion phase, determining a first most-significant-bit (MSB) of the converted output according to a comparison between output signals of the first capacitor DAC and the second capacitor DAC;
- defining one of the first capacitor DAC and the second capacitor DAC that has less output signal as a lower-voltage capacitor DAC, and the other of the first capacitor DAC and the second capacitor DAC as an un-switching capacitor DAC;
- switching all capacitors of the lower-voltage capacitor DAC to a power supply, the common voltage being greater than ground but less than the power supply;
- in an m-th conversion phase (1<m<n), determining an m-th MSB of the converted output according to a comparison between output signals of the first capacitor DAC and the second capacitor DAC;
- switching an (m−1)-th capacitor of the un-switching capacitor DAC according to a comparison between output signals of the lower-voltage capacitor DAC and the un-switching capacitor DAC;
- and
- in an n-th conversion phase, determining a least significant bit (LSB) of the converted output according to a comparison between output signals of the first capacitor DAC and the second capacitor DAC.
Dependencies are inferred from the claim text.