PLL circuit, semiconductor device including the same, and control method of PLL circuit

A PLL circuit comprising:

• a phase comparator that compares phases of a reference clock signal and a feedback clock signal;
• a first charge pump that generates a first current corresponding to a result of comparison by the phase comparator;
• a second charge pump that generates a second current corresponding to the result of comparison by the phase comparator;
• a first filter that generates a first control voltage obtained by removing ripple noise from a voltage generated based on the first current;
• a comparator that compares a voltage of a first node with a reference voltage;
• a switch section that selects and outputs the reference voltage to the first node and selects and outputs the second current to the second node in the case of a first mode and selects and outputs the second current to the first node and selects and outputs a result of comparison by the comparator to the second node in the case of a second mode;
• a second filter that generates a second control voltage by integrating a current flowing through the first node;
• a third filter that generates a third control voltage by integrating a current flowing through the second node;
• a voltage controlled oscillator that generates an output clock signal of a frequency corresponding to the first to the third control voltages;
• and
• a frequency divider that frequency-divides the output clock signal and outputs the frequency-divided output clock signal as the feedback clock signal.