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US 10,476,509 B2Granted
Time slotted bus system for multiple coupled digital phase-locked loops
AssigneeIntegrated Device Technology, Inc.
InventorMenno Spijker
Life of this patent
Estimating the term…
Abstract
An apparatus includes a plurality of digital phase-locked loops and a time slotted bus. The time slotted bus is configured to couple the plurality of digital phase-locked loops. The plurality of digital phase-locked loops may be configured to exchange parameters between two or more of the plurality of digital phase-locked loops using one or more time slots of the time slotted bus.
Claims20
An apparatus comprising:
- a plurality of digital phase-locked loops;
- and
- a time slotted bus coupling the plurality of digital phase-locked loops, wherein (i) each of said digital phase-locked loops comprises a bus interface module coupling said digital phase-locked loop to said time slotted bus, (ii) said plurality of digital phase-locked loops are configured to exchange parameters between two or more of said plurality of digital phase-locked loops using one or more respective time slots of a plurality of time slots of said time slotted bus, and (iii) at least two of said bus interface modules are configured to transmit parameter data to said time slotted bus during said one or more respective time slots of said plurality of time slots of said time slotted bus.
A method of coupling a plurality of digital phase-locked loops comprising:
- connecting each of said plurality of digital phase-locked loops to a time slotted bus;
- broadcasting addresses corresponding to predefined time slots of said time slotted bus;
- and
- exchanging parameters between two or more of said digital phase-locked loops using one or more of said predefined time slots of said time slotted bus associated with said two or more digital phase-locked loops.
1 more element
An apparatus comprising:
- a plurality of digital phase-locked loops;
- and
- a time slotted bus coupling the plurality of digital phase-locked loops, wherein said plurality of digital phase-locked loops are configured to exchange parameters between two or more of said plurality of digital phase-locked loops using one or more respective time slots of a plurality of time slots of said time slotted bus, wherein said time slotted bus comprises a first bus communicating parameter data and a second bus communicating address information identifying said time slots.
Dependencies are inferred from the claim text.