Apparatus for flexible electronic interfaces and associated methods
AssigneeAltera Corporation
InventorTony K. Ngai
Life of this patent
Estimating the term…
Abstract
A semiconductor die includes at least one flexible interface block. The flexible interface block includes at least one interconnect, and at least one buffer coupled to the at least one interconnect. The flexible interface block further includes a routing interface coupled to circuitry integrated in the semiconductor die, and a controller coupled to provide communication between the routing interface and the at least one buffer.
Claims20
A system, comprising:
- dynamic random access memory (DRAM) in a first semiconductor die disposed above an interposer;
- an interconnect, wherein the interconnect comprises a plurality of signal lines coupled between at least the first semiconductor die and a second semiconductor die, wherein the second semiconductor die is disposed above the interposer;
- and
- at least a portion of a field-programmable gate array (FPGA) disposed in the second semiconductor die, wherein the FPGA comprises:
- a hardened controller configured to control operation of the DRAM;
- and
- flexible routing circuitry configured to communicatively couple the hardened controller and circuitry in the FPGA, wherein the flexible routing circuitry is configured to route a data signal from the circuitry in the FPGA to the DRAM, from the DRAM to the circuitry in the FPGA, or both, and wherein the flexible routing circuitry is configured to selectively implement a signal path between the DRAM and the circuitry in the FPGA.
A method of manufacturing a device, comprising:
- disposing an integrated circuit device at least in part in a first semiconductor die;
- disposing second circuitry in a second semiconductor die;
- communicatively coupling an interconnect to at least the first semiconductor die and the second semiconductor die;
- communicatively coupling routing circuitry to first circuitry in the integrated circuit device, wherein the routing circuitry is configured to:
- select a subset of a set of data signals;
- and
- route the subset of the set of data signals from the first circuitry to the second circuitry;
- and
- communicatively coupling a hardened controller between the routing circuitry and the interconnect, wherein the first circuitry is communicatively coupled to the second circuitry via the routing circuitry, the hardened controller, and the interconnect.
A tangible, non-transitory, machine-readable medium, comprising machine-readable instructions that, when executed by one or more processors, cause the one or more processors to:
- display a representation of dynamic random access memory (DRAM) in a first semiconductor die disposed on an interposer and a representation of at least a portion of a field-programmable gate array (FPGA) disposed in a second semiconductor die, wherein the second semiconductor die is disposed on the interposer, and wherein displaying the representation of the DRAM comprises representing the DRAM as an embedded memory block of the FPGA;
- and
- configure the FPGA to route a data signal received at flexible routing circuitry of the FPGA from circuitry of the FPGA to the DRAM.
Dependencies are inferred from the claim text.