US 10,476,499 B2Granted

Low power consumption power-on reset circuit and reference signal circuit

AssigneeRichtek Technology Corporation

InventorsChin-Yuan Wei, Chih-Hsien Wang

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Abstract

A power-on reset (POR) circuit includes: a signal generator circuit for generating a first and a second signal according to an input voltage, and a comparator circuit. The comparator circuit, having a non-zero input offset, includes a first MOS transistor with a first conductive type and having a first conductive type gate and a first threshold voltage, and a second MOS transistor with a first conductive type and having a second conductive type gate and a second threshold voltage. The input offset relates to a difference between the first and the second threshold voltage. The first and the second signal control the first and the second MOS transistors respectively to generate a POR signal. When the input voltage exceeds a POR threshold which relates to a predetermined multiple or ratio of the input offset, the POR signal transits its state.

Claims19

Dependent claims

A power-on reset (POR) circuit, configured to operably generate a power-on reset signal, comprising:

a signal generator circuit, configured to operably generate a first signal and a second signal;
and
a comparator circuit, including a first input terminal and a second input terminal which are electrically connected to the first signal and the second signal respectively, wherein the comparator circuit compares the first signal and the second signal to generate a comparator output signal, wherein the POR circuit generates the POR signal according to the comparator output signal, the comparator circuit including:
a first MOS transistor of a first conductive type, coupled to the first input terminal, wherein the first MOS transistor includes a first conductive type gate and a first threshold voltage;
and
a second MOS transistor of the first conductive type, coupled to the second input terminal, wherein the second MOS transistor includes a second conductive type gate and a second threshold voltage;
wherein each of the first MOS transistor and the second MOS transistor is biased in a subthreshold region;
wherein the first signal and the second signal control the first MOS transistor and the second MOS transistor respectively to generate the comparator output signal;
wherein a differential input level of the comparator circuit includes a non-zero input offset, wherein the input offset relates to a difference between the first threshold voltage and the second threshold voltage;
wherein when the input voltage rises to exceed a first POR threshold, the comparator output signal transits from a first state to a second state;
wherein the first POR threshold substantially is a product of the input offset multiplied by a predetermined number;
wherein both the first MOS transistor and the second MOS transistor are of the same one of the following types of MOS transistors:
(1) enhancement mode MOS transistor, (2) depletion mode MOS transistor, or (3) native transistor.

10 more elements

A reference signal circuit, configured to operably generate a reference signal, comprising:

a signal generator circuit, including:
an active device, configured to operably convert an input voltage to the reference signal according to an amplifier output signal;
and
a voltage divider circuit, coupled to the reference signal, wherein the voltage divider circuit generates a first signal and a second signal according to the reference signal, wherein the first signal and the second signal are different divided voltages of the reference signal;
and
an amplifier circuit, including a first input terminal and a second input terminal which are electrically connected to the first signal and the second signal respectively, wherein the amplifier circuit amplifies a difference between the first signal and the second signal to generate the amplifier output signal, the amplifier circuit including:
a first MOS transistor of a first conductive type, coupled to the first input terminal, wherein the first MOS transistor includes a first conductive type gate and a first threshold voltage;
and
a second MOS transistor of the first conductive type, coupled to the second input terminal, wherein the second MOS transistor includes a second conductive type gate and a second threshold voltage;
wherein the first signal and the second signal control the first MOS transistor and the second MOS transistor respectively to generate the amplifier output signal;
wherein each of the first MOS transistor and the second MOS transistor is biased in a subthreshold region;
wherein a differential input level of the amplifier circuit includes a non-zero input offset, wherein the input offset relates to a difference between the first threshold voltage and the second threshold voltage;
wherein the amplifier circuit controls the active device to regulate the reference signal substantially to a product of the input offset multiplied by a predetermined number, wherein the predetermined number relates to a ratio between the first signal and the second signal;
wherein both the first MOS transistor and the second MOS transistor are of the same one of the following types of MOS transistors:
(1) enhancement mode MOS transistor, (2) depletion mode MOS transistor, or (3) native transistor.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/951,772Filed 12 Apr 2018
Priority: TW 106132811 A25 Sep 2017
Published: US 2019/0097623 A128 Mar 2019
Granted: 12 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H03K 17/223
Modifications for ensuring a predetermined initial state when the supply voltage has been applied: in field-effect transistor switches
G06F 1/24
Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00: resetting means
H03F 3/16
With semiconductor devices only: with field-effect devices
H03F 3/45183
Using MOSFET transistors as the active amplifying circuit: long tailed pairs