Selectable delay buffers and logic cells for dynamic voltage scaling in ultra low voltage designs
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJaskirat Bindra, Kumar Lalgudi
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Abstract
Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.
Claims20
A synchronous circuit including a logic gate configured to perform an operation on a data signal, a memory element configured to store the state of the operated-on data signal when triggered by a clock signal, a selection information generating circuit comprising a signal generator circuit for generating selection information using combinational logic, the combinational logic comprising an XNOR gate, and a selectable delay buffer for tuning a delay path in the synchronous circuit, the selectable delay buffer comprising:
- a first delay segment configured to pass one of the clock signal or the data signal to an input of the memory element within a first range of time delays;
- a second delay segment configured to pass the one of the clock signal or the data signal to the input of the memory element within a second range of time delays that is different from the first range;
- and
- a segment selection switch configured to selectively couple the delay segments to the input of the memory element based on received selection information from the selection information generating circuit, wherein the segment selection switch is configured to select the first delay segment to complete a delay path at a first supply voltage level and the segment selection switch is configured to select the second delay segment to complete the delay path at a second supply voltage level.
A method in a synchronous circuit having a selectable delay buffer for tuning a delay path in the synchronous circuit, the method comprising:
- comparing the voltage level of a voltage source to one or more reference voltage levels;
- generating selection information using combinational logic based on the voltage level comparison, the combinational logic comprising an XNOR gate;
- selecting a first delay segment in a selectable delay buffer when the voltage level comparison indicates use of the first delay segment;
- selecting a second delay segment in the selectable delay buffer when the voltage level comparison indicates use of the second delay segment;
- and
- coupling the selected delay segment into a delay path in the synchronous circuit.
A synchronous circuit including a logic gate configured to perform an operation on a data signal, a first memory element configured to receive the data signal and a clock signal, a second memory element configured to store the state of the operated-on data signal when triggered by a delayed clock signal, a selection information generating circuit comprising a signal generator circuit for generating the selection information using combinational logic, the combinational logic comprising an XNOR gate, and a selectable delay buffer for tuning a delay path in the synchronous circuit, the selectable delay buffer comprising:
- a first delay segment configured to pass one of the clock signal or the data signal to an input of the second memory element within a first range of time delays;
- a second delay segment configured to pass the one of the clock signal or the data signal to the input of the second memory element within a second range of time delays that is different from the first range;
- and
- a segment selection switch configured to selectively couple the delay segments to the input of the second memory element based on received selection information from the selection information generating circuit, wherein the segment selection switch is configured to select the first delay segment to complete a delay path at a first supply voltage level and the segment selection switch is configured to select the second delay segment to complete the delay path at a second supply voltage level.
Dependencies are inferred from the claim text.