US 10,476,487 B2Granted

Electronic comparison systems

AssigneePurdue Research Foundation

InventorsKaushik Roy, Mrigank Sharad

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Abstract

An electronic comparison system includes input stages that successively provide bits of code words. One-shots connected to respective stages successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then provide a second, different bit value. An enable circuit provides the enable signal if at least one of the one-shots is providing the first bit value. A neural network system includes a crossbar with row and column electrodes and resistive memory elements at their intersections. A writing circuit stores weights in the elements. A signal source applies signals to the row electrodes. Comparators compare signals on the column electrodes to corresponding references using domain-wall neurons and store bit values in CMOS latches by comparison with a threshold.

Claims20

Dependent claims

A system, comprising:

a crossbar array having a plurality of row electrodes, a plurality of column electrodes, and a plurality of resistive memory elements, each memory element connected to one of the row electrodes and one of the column electrodes;
a writing circuit configured to store selected weights in the resistive memory elements;
a signal source configured to apply a plurality of test electrical signals to respective ones of the row electrodes;
a reference source configured to provide one or more reference electrical signal(s), each of the reference electrical signal(s) comprising a respective reference current or a respective reference voltage;
a plurality of domain-wall neurons;
a plurality of latches;
and
a plurality of comparators, each configured to compare an electrical signal on a respective one of the column electrodes to a corresponding one of the reference electrical signal(s), wherein each comparator comprises:
a respective domain-wall neuron of the plurality of domain-wall neurons, the respective domain-wall neuron connected to the respective column electrode and to the reference source;
and
a latch of the plurality of latches, the respective latch configured to compare an output of the respective domain-wall neuron with a selected threshold and store a respective bit value according to the result of the comparison,
wherein:
the reference source comprises:
a reference controller programmed to sequence through a selected number of bits, starting with a most-significant bit of the selected number of bits;
and
a plurality of reference circuits, each configured to provide one of the reference electrical signal(s) to a respective one of the comparators;
each reference circuit comprises:
a register configured to hold respective values for the selected number of bits;
and
a signal generator that provides the respective one of the reference electrical signals in response to the values in the register;
and
the reference controller is configured to successively update the bits of each of the registers in the sequence according to the stored bit value in the respective one of the comparators.

19 more elements

A system, comprising:

a crossbar array having a plurality of row electrodes, a plurality of column electrodes, and a plurality of resistive memory elements, each memory element connected to one of the row electrodes and one of the column electrodes;
a writing circuit configured to store selected weights in the resistive memory elements;
a signal source configured to apply a plurality of test electrical signals to respective ones of the row electrodes;
a reference source configured to provide one or more reference electrical signal(s);
a plurality of domain-wall neurons;
a plurality of latches;
and
a plurality of comparators, each configured to compare an electrical signal on a respective one of the column electrodes to a corresponding one of the reference electrical signal(s), wherein each comparator includes:
a respective domain-wall neuron of the plurality of domain-wall neurons, the respective domain-wall neuron connected to the respective column electrode and to the reference source;
and
a latch of the plurality of latches, the respective latch configured to compare an output of the respective domain-wall neuron with a selected threshold and store a respective bit value according to the result of the comparison,
wherein:
the reference source includes:
a reference controller programmed to sequence through a selected number of bits, starting with a most-significant bit of the selected number of bits;
and
a plurality of reference circuits, each configured to provide one of the reference electrical signal(s) to a respective one of the comparators;
each reference circuit includes:
a register configured to hold respective values for the selected number of bits;
and
a signal generator that provides the respective one of the reference electrical signals in response to the values in the register;
and
the reference controller is configured to successively update the bits of each of the registers in the sequence according to the stored bit value in the respective one of the comparators.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/801,535Filed 2 Nov 2017 · continuation
Priority: 27 May 2014
Published: US 2018/0069536 A18 Mar 2018
Granted: 12 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H03K 3/356104
Bistable circuits: using complementary field-effect transistors
G06N 3/063
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons: using electronic means
G11C 11/16
Using magnetic elements: using elements in which the storage effect is based on magnetic spin effect
G11C 11/161
Using elements in which the storage effect is based on magnetic spin effect: details concerning the memory cell structure, e.g. the layers of the…

Family

Application14/287,701Parent of this division · filed 27 May 2014
Application15/334,649Parent of this continuation · filed 26 Oct 2016
US 9,489,618 B2Parent of this division · filed 8 Nov 2016
US 2018/0069536 A1Pre-grant publication · published 8 Mar 2018
US 9,813,048 B2Parent of this continuation
Application15/334,649Parent of this division
US 2015/0347896 A1Published application
US 2017/0047913 A1Published application
US 10,476,487 B2This patent

From the US filing history. Foreign family members aren’t listed.