Semiconductor package having an isolation wall to reduce electromagnetic coupling
AssigneeNXP USA, Inc.
InventorsMargaret A. Szymanowski, Sarmad K. Musa, Fernando A. Santos, Mahesh K. Shah
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Abstract
A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.
Claims14
A method of fabricating a semiconductor device, the method comprising:
- forming a first circuit on a substrate;
- forming a second circuit on a substrate adjacent to the first circuit;
- forming a lead frame from an electrically conductive sheet, wherein the lead frame includes first and second leads within a plane of the electrically conductive sheet and a wall section that is transverse to the plane of the electrically conductive sheet;
- electrically coupling the first circuit to the first lead with a first wire bond array;
- electrically coupling the second circuit to the second lead with a second wire bond array;
- and
- locating the wall section between the first circuit and the second circuit, the wall section extending above a height of the first and second wire bond arrays, and the wall section being configured to reduce electromagnetic coupling between the first circuit and the second circuit during an operation of the semiconductor device.
A method of fabricating a Doherty amplifier, the method comprising:
- forming a carrier amplifier on a substrate, the carrier amplifier including a first transistor and a first wire bond array electrically coupled between the first transistor and a first lead;
- forming a peaking amplifier on the substrate adjacent to the carrier amplifier, the peaking amplifier including a second transistor and a second wire bond array electrically coupled between the second transistor and a second lead;
- and
- locating an isolation wall formed of electrically conductive material between the carrier amplifier and the peaking amplifier above a surface of the substrate, the isolation wall formed of a body of material that is oriented perpendicular to the surface of the substrate and extending above a height of the first and second wire bond arrays, the isolation wall being configured to reduce an electromagnetic coupling between the carrier amplifier and the peaking amplifier during an operation of the Doherty amplifier, wherein the isolation wall is formed by a section of a lead frame that also includes the first lead and the second lead.
Dependencies are inferred from the claim text.