Back to results
US 10,476,016 B2Granted
Ambipolar synaptic devices
AssigneeInternational Business Machines Corporation
InventorsAli Afzali-Ardakani, Tze-Chiang Chen, Kailash Gopalakrishnan, Bahman Hekmatshoartabari
Life of this patent
Estimating the term…
Abstract
Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
Claims20
A method comprising:
- providing a synaptic device including a first structure configured for injecting both electrons and holes into a semiconductor layer and traps for trapping both electrons and holes, the first structure including a source/drain region adjoining the semiconductor layer and containing n+ and p+ regions;
- receiving an electrical signal at the synaptic device, thereby causing the source/drain region of the first structure to inject one of electrons and holes into the semiconductor layer, and
- effecting net negative charge trapping or net positive charge trapping within the traps upon injection of the one of electrons and holes into the semiconductor layer.
A method comprising:
- providing a synaptic device including a first structure configured for injecting both electrons and holes into a semiconductor layer and traps for trapping both electrons and holes, a gate electrically coupled to the semiconductor layer through a gate dielectric layer, the semiconductor layer being comprised of semiconductor materials having different bandgaps and forming quantum wells comprising the traps;
- receiving an electrical signal at the synaptic device, thereby causing a change in gate voltage, the change in gate voltage causing the first structure to inject one of electrons and holes into the semiconductor layer, and
- effecting net negative charge trapping or net positive charge trapping within the traps upon injection of the one of electrons and holes into the semiconductor layer.
A method comprising:
- providing a synaptic device including a first structure configured for injecting both electrons and holes into a semiconductor layer and traps for trapping both electrons and holes;
- receiving an electrical signal at the synaptic device, thereby causing the source/drain region of the first structure to inject one of electrons and holes into the semiconductor layer, and
- effecting net negative charge trapping or net positive charge trapping within the traps upon injection of the one of electrons and holes into the semiconductor layer, wherein the synaptic device further includes:
- a gate electrically coupled to the semiconductor layer through a gate dielectric layer or a gate barrier layer;
- a pair of source/drain regions adjoining the semiconductor layer, the first structure comprising one of the source/drain regions, and
- a plurality of quantum wells within the semiconductor layer and between the source/drain regions, the plurality of quantum wells being configured for effecting both net negative charge trapping and net positive charge trapping, the traps comprising the plurality of quantum wells;
- further including causing a change in gate voltage upon receipt of the electrical signal, the change in gate voltage causing the injection of one of the electrons and holes into the semiconductor layer.
4 more elements
A method comprising:
- providing a synaptic device including a semiconductor layer, a first structure configured for injecting both electrons and holes into the semiconductor layer, traps for trapping both electrons and holes, and a gate electrically coupled to the semiconductor layer through a gate dielectric layer, the semiconductor layer including lattice-matched or nearly lattice-matched single-crystalline quantum wells or quantum dots comprising the traps;
- receiving an electrical signal at the synaptic device, thereby causing a change in gate voltage, the change in gate voltage causing the injection of one of the electrons and holes into the semiconductor layer, and
- effecting net negative charge trapping or net positive charge trapping within the traps upon injection of the one of electrons and holes into the semiconductor layer.
A method comprising:
- providing a synaptic device including a semiconductor layer, a first structure configured for injecting both electrons and holes into the semiconductor layer, the first structure including a source/drain region adjoining the semiconductor layer and containing n+ and p+ regions, traps for trapping both electrons and holes, and a gate electrically coupled to the semiconductor layer through a gate dielectric layer;
- receiving an electrical signal at the synaptic device, thereby causing a change in gate voltage, the change in gate voltage causing the injection of one of the electrons and holes by the source/drain region into the semiconductor layer, and
- effecting net negative charge trapping or net positive charge trapping within the traps upon injection of the one of electrons and holes into the semiconductor layer.
A method comprising:
- providing a synaptic device including a semiconductor layer, a first structure configured for injecting both electrons and holes into the semiconductor layer, traps for trapping both electrons and holes, and a gate electrically coupled to the semiconductor layer through a gate dielectric layer, the semiconductor layer including ambipolar deep traps comprising the traps;
- receiving an electrical signal at the synaptic device, thereby causing a change in gate voltage, the change in gate voltage causing the injection of one of the electrons and holes by the source/drain region into the semiconductor layer, and
- effecting net negative charge trapping or net positive charge trapping within the traps upon injection of the one of electrons and holes into the semiconductor layer.
Dependencies are inferred from the claim text.