US 10,475,999 B2Granted

Metal landing on top electrode of RRAM

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChih-Yang Chang, Wen-Ting Chu

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Abstract

Some embodiments relate to a method. A semiconductor substrate is received. The semiconductor substrate has an interconnect structure disposed over a memory region and a logic region of the semiconductor substrate. A bottom electrode and a top electrode are formed over the interconnect structure over the memory region. The bottom electrode is coupled to a lower metal layer in the interconnect structure, and the bottom and top electrode are separated from one another by a data storage or dielectric layer. An interlayer dielectric (ILD) layer is formed over the top electrode. A trench opening having vertical or substantially vertical sidewalls is formed in the ILD layer and exposes an upper surface of the top electrode. An upper metal layer is formed in the trench opening and is in direct contact with the top electrode.

Claims20

Dependent claims

A method, comprising:

receiving a semiconductor substrate having an interconnect structure disposed over a memory region and a logic region of the semiconductor substrate;
forming a bottom electrode and a top electrode over the interconnect structure over the memory region, wherein the bottom electrode is coupled to a lower metal layer in the interconnect structure and wherein the bottom and top electrode are separated from one another by a data storage or dielectric structure;
wherein forming the bottom electrode and the top electrode comprises:
forming an etch stop layer over an upper surface of a dielectric layer in the interconnect structure and over an upper surface of a metal body in the interconnect structure, the upper surface of the dielectric layer being co-planar with the upper surface of the metal body;
forming an opening through the etch stop layer to expose an upper surface of the metal body;
and
forming a bottom electrode layer over the etch stop layer, the bottom electrode layer being coupled to the metal body;
forming an interlayer dielectric (ILD) layer over the top electrode;
forming a trench opening having vertical or substantially vertical sidewalls in the ILD layer and which exposes an upper surface of the top electrode;
and
forming an upper metal layer in the trench opening, the upper metal layer being in direct contact with the top electrode.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/831,921Filed 5 Dec 2017 · division
Priority: 27 Oct 2015
Published: US 2018/0097177 A15 Apr 2018
Granted: 12 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10N 70/841
Constructional details of multistable switching devices: electrodes
H10B 63/30
Resistance change memory devices, e.g. resistive RAM [ReRAM] devices: comprising selection components having three or more electrodes, e.g.…
H10N 70/011
Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching: manufacture or…
H10N 70/063
Shaping switching materials: by etching of pre-deposited switching material layers, e.g. lithography

Family

Application14/923,589Parent of this division · filed 27 Oct 2015
US 2018/0097177 A1Pre-grant publication · published 5 Apr 2018
US 9,847,481 B2Parent of this division
US 2017/0117467 A1Published application
US 10,475,999 B2This patent

From the US filing history. Foreign family members aren’t listed.