Pillar contact extension and method for producing the same

A device comprising:

• an interlayer dielectric (ILD) with a memory region and a logic region;
• a metal layer in the memory region and in the logic region;
• pillar-shaped conductors over the metal layer only in the memory region;
• a pillar contact extension atop of each pillar-shaped conductor;
• a first low-K layer over the metal layer and the ILD and surrounding each pillar contact extension, the first low-K layer over the memory region and an upper surface of each pillar contact extension being coplanar;
• a second low-K layer over the first low-K layer and pillar contact extensions;
• and
• a BEOL contact at least atop of each pillar contact extension in the memory region and the metal layer in the logic region and through the second low-K layer and the first low-K layer, respectively.

A method comprising:

• forming a photoresist layer over an oxide layer formed over a first low-K layer formed over an interlayer dielectric (ILD) having a copper (Cu) layer in a memory region and in a logic region and metal tunnel junction (MTJ) structures formed atop of the Cu layer only in the memory region;
• forming a trench through the photoresist layer down to the oxide layer over each MTJ;
• extending the trench through the oxide layer and the first low-K layer down to an upper surface of each MTJ;
• forming a tantalum nitride (TaN) layer over the first low-K layer, filling the trench entirely;
• chemical-mechanical planarizing (CMP) the TaN layer until the TaN layer and the oxide layer are removed from over the logic region, a TaN pillar contact extension formed atop of each MTJ;
• forming a second low-K layer over the TaN layer and the first low-K layer;
• and
• forming a back-end-of-line (BEOL) contact down to at least each TaN pillar contact extension in the memory region and the Cu layer in the logic region through the second low-K layer and the first low-K layer, respectively.