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US 10,475,920 B2Granted
Semiconductor device and semiconductor device manufacturing method
AssigneeMitsubishi Electric Corporation
InventorsKoji Sadamatsu, Shiro Hino
Life of this patent
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Abstract
A drift layer is made of a wide bandgap semiconductor. First well regions are formed on the drift layer. A source region is formed on each of the first well regions. A gate insulating film is formed on the first well regions. A first electrode is in contact with the source regions, and has diode characteristics allowing unipolar conduction to the drift layer between the first well regions. A second well region is formed on the drift layer. A second electrode is in contact with the second well region, and separated from a gate electrode and the first electrode.
Claims14
A semiconductor device, comprising:
- a semiconductor substrate having a first conductivity type;
- a drift layer having said first conductivity type, said drift layer being formed on said semiconductor substrate and made of a wide bandgap semiconductor;
- a plurality of first well regions being formed on said drift layer and having a second conductivity type different from said first conductivity type;
- a source region being separated from said drift layer by one of said plurality of first well regions and having said first conductivity type, said source region being formed on each of said plurality of first well regions;
- a gate insulating film formed on each of said plurality of first well regions;
- a gate electrode formed above said gate insulating film;
- a first electrode being ohmic-connected to said source regions, and having diode characteristics allowing unipolar conduction to said drift layer through a spaced-apart region between adjacent first well regions of said plurality of first well regions, said spaced-apart region having said first conductivity type;
- at least one second well region being formed on said drift layer to be separated from said plurality of first well regions, and having said second conductivity type, said gate electrode being arranged above said at least one second well region;
- a second electrode being ohmic-connected to said at least one second well region and not in direct contact with any semiconductor region having said first conductivity type, insulated from said gate electrode, and separated from said first electrode, said second electrode being large enough to place a probe needle;
- and
- a third electrode electrically connected to said semiconductor substrate,
- wherein said gate electrode includes an electrode portion and a wiring layer that has a resistivity lower than a resistivity of said electrode portion, and
- said wiring layer is vertically above a part of said at least one second well.
10 more elements
A method for manufacturing a semiconductor device, comprising:
- forming
- a semiconductor substrate having a first conductivity type,
- a drift layer having said first conductivity type, said drift layer being formed on said semiconductor substrate and made of a wide bandgap semiconductor,
- a plurality of first well regions being formed on said drift layer and having a second conductivity type different from said first conductivity type,
- a source region being separated from said drift layer by one of said plurality of first well regions and having said first conductivity type, said source region being formed on each of said plurality of first well regions,
- a gate insulating film formed on each of said plurality of first well regions,
- a gate electrode formed above said gate insulating film,
- a first electrode being in contact with said source regions, and having diode characteristics allowing unipolar conduction to said drift layer through a spaced-apart region between adjacent first well regions of said plurality of first well regions, said spaced-apart region having said first conductivity type,
- at least one second well region being formed on said drift layer to be separated from said plurality of first well regions, and having said second conductivity type, said gate electrode being arranged above said at least one second well region,
- a second electrode being in contact with said at least one second well region and not in direct contact with any semiconductor region having said first conductivity type, insulated from said gate electrode, and separated from said first electrode, and
- a third electrode electrically connected to said semiconductor substrate;
- and
- forward biasing a p-n junction between said at least one second well region and said drift layer with application of a voltage between said second electrode and said third electrode, said voltage being lower than a voltage between said first electrode and said third electrode,
- wherein said gate electrode includes an electrode portion and a wiring layer that has a resistivity lower than a resistivity of said electrode portion, and
- said wiring layer is vertically above a part of said at least one second well.
12 more elements
Dependencies are inferred from the claim text.