Method of producing an integrated power transistor circuit having a current-measuring cell

A method for producing an integrated power transistor circuit, the method comprising:

• providing a semiconductor substrate comprising a cell array and a region outside the cell array;
• forming a plurality of transistor cells of the cell array connected in parallel to form a power transistor, each of the transistor cells having a doped region formed in the semiconductor substrate and adjoining a first surface on a first side of the semiconductor substrate, a channel region and a gate conductor structure;
• forming an electrode structure on the first side of the semiconductor substrate in a projection of the cell array orthogonal to the first surface;
• forming a gate electrode on the first side of the semiconductor substrate outside the cell array, the gate electrode being physically separated from and electrically connected to each gate conductor structure, wherein each gate conductor structure extends in a longitudinal direction from the cell array into the region outside the cell array and under the gate electrode;
• forming a contact structure on the first side of the semiconductor substrate and electrically conductively connected to the doped region and the electrode structure, the contact structure having a first section between the electrode structure and the semiconductor substrate above the cell array, a second section above the region outside the cell array and connecting the first section to an interface structure in the region outside the cell array, and a third section arranged on the first side of the semiconductor substrate outside the cell array and between the gate electrode and the semiconductor substrate, the third section being electrically insulated and physically separated from the first and the second sections;
• forming a dielectric layer between the first surface and the contact structure in both the cell array and the region outside the cell array;
• and
• forming plated-through holes in the cell array which extend through the dielectric layer and electrically connect the contact structure to the doped region and the channel region of each transistor cell of the power transistor,
• wherein the dielectric layer has a bottom surface in the cell array and the region outside the cell array,
• wherein the bottom surface is located in the same plane in both the cell array and the region outside the cell array,
• wherein the first surface contacts the bottom surface of the dielectric layer.