Gate arrangements in quantum dot devices

A quantum computing device, comprising:

• a quantum processing device, wherein the quantum processing device includes a quantum well stack, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, a layer of gate dielectric shared by at least two gates of the plurality of gates, a gate wall on the layer of gate dielectric between at least two gates, wherein the gate wall includes a first dielectric material and a second dielectric material different from the first dielectric material;
• and
• a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the plurality of gates.