Semiconductor device having an insulated gate bipolar transistor arrangement

A semiconductor device comprising an insulated gate bipolar transistor arrangement,

• the insulated gate bipolar transistor arrangement comprising at least a first configuration region of emitter-side insulated gate bipolar transistor structures, wherein each emitter-side insulated gate bipolar transistor structure of the first configuration region comprises a body area, a source area, and a gate, and a second configuration region of emitter-side insulated gate bipolar transistor structures, wherein each emitter-side insulated gate bipolar transistor structure of the second configuration region comprises a body area, a source area, and a gate, wherein the first configuration region and the second configuration region are arranged at a main surface of a semiconductor substrate of the semiconductor device,
• wherein the insulated gate bipolar transistor arrangement comprises a collector layer and a drift layer which are part of the semiconductor substrate, wherein the collector layer is arranged at a backside surface of the semiconductor substrate of the semiconductor device and the drift layer is arranged between the collector layer and the emitter-side insulated gate bipolar transistor structures of the first configuration region and the second configuration region,
• wherein the collector layer comprises at least a first doping region laterally adjacent to a second doping region, wherein the first doping region and the second doping region comprise different charge carrier life times, different conductivity types or different doping concentrations,
• wherein the first configuration region is located with at least a partial lateral overlap to the first doping region and the second configuration region is located with at least a partial lateral overlap to the second doping region, and
• wherein the emitter-side insulated gate bipolar transistor structures of the first configuration region and the second configuration region comprise a plurality of body areas, a plurality of source areas and a plurality of gates each, wherein the plurality of source areas and the drift layer comprise at least mainly a first conductivity type, wherein the plurality of body areas and the collector layer comprise at least mainly a second conductivity type, wherein the plurality of gates are arranged so that the gates are capable of causing a conductive channel between the source areas and the drift layer through the body areas,
• wherein the emitter-side insulated gate bipolar transistor structures of the first configuration region and the second configuration region comprise a plurality of trenches reaching vertically through a body layer comprising the plurality of body regions, wherein the gates are arranged in trenches of the plurality of trenches, and
• wherein an average distance of neighboring trenches located in the first configuration region is different from an average distance of neighboring trenches located in the second configuration region, and wherein the differences in average distance of neighboring trenches compensates for the difference in density of free charge carriers during an on-state of the insulated gate bipolar transistor arrangement caused by the different charge carrier life times, different conductivity types or different doping concentrations.

A semiconductor device comprising an insulated gate bipolar transistor arrangement,

• the insulated gate bipolar transistor arrangement comprising at least a first configuration region of emitter-side insulated gate bipolar transistor structures, wherein each emitter-side insulated gate bipolar transistor structure of the first configuration region comprises a body area, a source area, and a gate, and a second configuration region of emitter-side insulated gate bipolar transistor structures, wherein each emitter-side insulated gate bipolar transistor structure of the second configuration region comprises a body area, a source area, and a gate, wherein the first configuration region and the second configuration region are arranged at a main surface of a semiconductor substrate of the semiconductor device,
• wherein the insulated gate bipolar transistor arrangement comprises a collector layer and a drift layer which are part of the semiconductor substrate, wherein the collector layer is arranged at a backside surface of the semiconductor substrate of the semiconductor device and the drift layer is arranged between the collector layer and the emitter-side insulated gate bipolar transistor structures of the first configuration region and the second configuration region,
• wherein the collector layer comprises at least a first doping region laterally adjacent to a second doping region, wherein the first doping region and the second doping region comprise different charge carrier life times, different conductivity types or different doping concentrations,
• wherein the first configuration region is located with at least a partial lateral overlap to the first doping region and the second configuration region is located with at least a partial lateral overlap to the second doping region, and
• wherein the emitter-side insulated gate bipolar transistor structures of the first configuration region and the second configuration region comprise a plurality of body areas, a plurality of source areas and a plurality of gates each, wherein the plurality of source areas and the drift layer comprise at least mainly a first conductivity type, wherein the plurality of body areas and the collector layer comprise at least mainly a second conductivity type, wherein the plurality of gates are arranged so that the gates are capable of causing a conductive channel between the source areas and the drift layer through the body areas,
• wherein the emitter-side insulated gate bipolar transistor structures of the first configuration region and the second configuration region comprise a plurality of trenches reaching vertically through a body layer comprising the plurality of body regions, wherein the gates are arranged in trenches of the plurality of trenches, and
• wherein each trench of the plurality of trenches surrounds a body region of the plurality of body regions, wherein an average distance of neighboring body regions surrounded by trenches located in the first configuration region is different from an average distance of neighboring body regions surrounded by trenches located in the second configuration region, and wherein the differences in average distance of neighboring body regions compensates for the difference in density of free charge carriers during an on-state of the insulated gate bipolar transistor arrangement caused by the different charge carrier life times, different conductivity types or different doping concentrations.